252     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());  in CopyAndMoveSuccessors()  local
253     for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {  in CopyAndMoveSuccessors()
254       if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {  in CopyAndMoveSuccessors()
259     if (MCID.isCommutable())  in CopyAndMoveSuccessors()
425   const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());  in getPhysicalRegisterVT()  local
426   assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");  in getPhysicalRegisterVT()
427   unsigned NumRes = MCID.getNumDefs();  in getPhysicalRegisterVT()
428   for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {  in getPhysicalRegisterVT()
503     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());  in DelayForLiveRegsBottomUp()  local
504     if (!MCID.ImplicitDefs)  in DelayForLiveRegsBottomUp()
506     for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {  in DelayForLiveRegsBottomUp()