299     bool fixupImmediateBr(ImmBranch &Br);
300     bool fixupConditionalBr(ImmBranch &Br);
301     bool fixupUnconditionalBr(ImmBranch &Br);
1529 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {  in fixupImmediateBr()  argument
1530   MachineInstr *MI = Br.MI;  in fixupImmediateBr()
1534   if (isBBInRange(MI, DestBB, Br.MaxDisp))  in fixupImmediateBr()
1537   if (!Br.isCond)  in fixupImmediateBr()
1538     return fixupUnconditionalBr(Br);  in fixupImmediateBr()
1539   return fixupConditionalBr(Br);  in fixupImmediateBr()
1547 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {  in fixupUnconditionalBr()  argument
1548   MachineInstr *MI = Br.MI;  in fixupUnconditionalBr()
1554   Br.MaxDisp = (1 << 21) * 2;  in fixupUnconditionalBr()
1570 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {  in fixupConditionalBr()  argument
1571   MachineInstr *MI = Br.MI;  in fixupConditionalBr()
1595         BMI->getOpcode() == Br.UncondBr) {  in fixupConditionalBr()
1604       if (isBBInRange(MI, NewDest, Br.MaxDisp)) {  in fixupConditionalBr()
1634   Br.MI = &MBB->back();  in fixupConditionalBr()
1637     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)  in fixupConditionalBr()
1640     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);  in fixupConditionalBr()
1642   unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);  in fixupConditionalBr()
1643   ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));  in fixupConditionalBr()
1752     ImmBranch &Br = ImmBranches[i];  in optimizeThumb2Branches()  local
1753     unsigned Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1773       MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1774       if (isBBInRange(Br.MI, DestBB, MaxOffs)) {  in optimizeThumb2Branches()
1775         DEBUG(dbgs() << "Shrink branch: " << *Br.MI);  in optimizeThumb2Branches()
1776         Br.MI->setDesc(TII->get(NewOpc));  in optimizeThumb2Branches()
1777         MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1785     Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1791     if (!Br.MI->killsRegister(ARM::CPSR))  in optimizeThumb2Branches()
1796     ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);  in optimizeThumb2Branches()
1803     MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1806     unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;  in optimizeThumb2Branches()
1809       MachineBasicBlock::iterator CmpMI = Br.MI;  in optimizeThumb2Branches()
1810       if (CmpMI != Br.MI->getParent()->begin()) {  in optimizeThumb2Branches()
1818             MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1819             DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);  in optimizeThumb2Branches()
1821               BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))  in optimizeThumb2Branches()
1822               .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());  in optimizeThumb2Branches()
1824             Br.MI->eraseFromParent();  in optimizeThumb2Branches()
1825             Br.MI = NewBR;  in optimizeThumb2Branches()