269   SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270   SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271   SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274   SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275   SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276   SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1445 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {  in PairSRegs()  argument
1446   DebugLoc dl = V0.getNode()->getDebugLoc();  in PairSRegs()
1451   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in PairSRegs()
1457 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {  in PairDRegs()  argument
1458   DebugLoc dl = V0.getNode()->getDebugLoc();  in PairDRegs()
1462   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in PairDRegs()
1468 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {  in PairQRegs()  argument
1469   DebugLoc dl = V0.getNode()->getDebugLoc();  in PairQRegs()
1473   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in PairQRegs()
1479 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,  in QuadSRegs()  argument
1481   DebugLoc dl = V0.getNode()->getDebugLoc();  in QuadSRegs()
1488   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in QuadSRegs()
1495 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,  in QuadDRegs()  argument
1497   DebugLoc dl = V0.getNode()->getDebugLoc();  in QuadDRegs()
1503   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in QuadDRegs()
1510 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,  in QuadQRegs()  argument
1512   DebugLoc dl = V0.getNode()->getDebugLoc();  in QuadQRegs()
1518   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in QuadQRegs()
1780       SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
1783         SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);  in SelectVST()
1791         SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVST()
1833   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
1839   SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVST()
1945   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVLDSTLane()  local
1949       SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);  in SelectVLDSTLane()
1951       SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);  in SelectVLDSTLane()
1958       SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
1960       SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2083   SDValue V0 = N->getOperand(FirstTblReg + 0);  in SelectVTBL()  local
2086     RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);  in SelectVTBL()
2094     RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVTBL()
3292     SDValue V0 = N->getOperand(0);  in Select()  local
3294     SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);  in Select()