Lines Matching refs:is64BitVector
279 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1527 bool is64BitVector) { in GetVLDSTAlign() argument
1529 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1605 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1606 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()
1632 if (!is64BitVector) in SelectVLD()
1648 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1649 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1714 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1742 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
1743 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVST()
1774 if (is64BitVector || NumVecs <= 2) { in SelectVST()
1778 } else if (is64BitVector) { in SelectVST()
1800 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVST()
1890 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
1924 if (!is64BitVector) in SelectVLDSTLane()
1948 if (is64BitVector) in SelectVLDSTLane()
1957 if (is64BitVector) in SelectVLDSTLane()
1968 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLDSTLane()
1980 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()