Lines Matching refs:v8i16
1025 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1320 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1993 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2035 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
3068 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3071 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3102 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3103 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3117 v8i8, v8i16, OpNode>;
3134 v8i8, v8i16, IntOp>;
3148 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3149 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3180 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3182 v8i16, v8i16, OpNode, Commutable>;
3191 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3229 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3231 v8i16, v8i16, IntOp, Commutable>;
3250 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3252 v8i16, v8i16, IntOp>;
3266 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3267 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3340 v8i8, v8i16, IntOp, Commutable>;
3356 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3358 v8i16, v8i8, OpNode, Commutable>;
3380 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3382 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3422 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3424 v8i16, v8i8, IntOp, Commutable>;
3431 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3433 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3448 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3450 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3477 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3478 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3491 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3492 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3516 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3517 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3538 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3539 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3551 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3552 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3593 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3594 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3601 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3602 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3628 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3629 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3630 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3651 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3652 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3653 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3687 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3688 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3724 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3725 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3763 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3764 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3803 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3804 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3839 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3840 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3856 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3857 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3877 v8i8, v8i16, shr_imm8, OpNode> {
3959 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3960 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3961 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3985 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3986 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3988 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4007 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4008 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4010 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4028 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4058 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4059 (mul (v8i16 QPR:$src2),
4060 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4061 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4116 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4117 (mul (v8i16 QPR:$src2),
4118 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4119 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4330 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4381 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4420 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4707 v8i16, v8i8, imm8, NEONvshlli>;
4828 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4845 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4911 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4994 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5002 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5057 [(set QPR:$V, (vector_insert (v8i16 QPR:$src1),
5096 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5097 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5120 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5159 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5178 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5179 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5209 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5288 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5309 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5337 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5391 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5599 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5604 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5608 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5609 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5610 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5611 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5612 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5615 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5620 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5625 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5633 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
5752 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16