Lines Matching refs:getReg
88 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
89 << ", " << getRegisterName(MO1.getReg()); in printInst()
91 O << ", " << getRegisterName(MO2.getReg()); in printInst()
107 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
108 << ", " << getRegisterName(MO1.getReg()); in printInst()
123 MI->getOperand(0).getReg() == ARM::SP && in printInst()
135 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
139 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; in printInst()
146 MI->getOperand(0).getReg() == ARM::SP && in printInst()
158 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
162 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}"; in printInst()
170 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
181 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
192 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst()
194 if (MI->getOperand(i).getReg() == BaseReg) in printInst()
210 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && in printInst()
211 MI->getOperand(1).getReg() == ARM::R8) { in printInst()
226 unsigned Reg = Op.getReg(); in printOperand()
269 O << getRegisterName(MO1.getReg()); in printSORegRegOperand()
277 O << ' ' << getRegisterName(MO2.getReg()); in printSORegRegOperand()
286 O << getRegisterName(MO1.getReg()); in printSORegImmOperand()
307 O << "[" << getRegisterName(MO1.getReg()); in printAM2PreOrOffsetIndexOp()
309 if (!MO2.getReg()) { in printAM2PreOrOffsetIndexOp()
320 << getRegisterName(MO2.getReg()); in printAM2PreOrOffsetIndexOp()
335 O << "[" << getRegisterName(MO1.getReg()) << "], "; in printAM2PostIndexOp()
337 if (!MO2.getReg()) { in printAM2PostIndexOp()
346 << getRegisterName(MO2.getReg()); in printAM2PostIndexOp()
358 O << "[" << getRegisterName(MO1.getReg()) << ", " in printAddrModeTBB()
359 << getRegisterName(MO2.getReg()) << "]"; in printAddrModeTBB()
366 O << "[" << getRegisterName(MO1.getReg()) << ", " in printAddrModeTBH()
367 << getRegisterName(MO2.getReg()) << ", lsl #1]"; in printAddrModeTBH()
395 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
404 << getRegisterName(MO1.getReg()); in printAddrMode2OffsetOperand()
422 O << "[" << getRegisterName(MO1.getReg()) << "], "; in printAM3PostIndexOp()
424 if (MO2.getReg()) { in printAM3PostIndexOp()
426 << getRegisterName(MO2.getReg()); in printAM3PostIndexOp()
442 O << '[' << getRegisterName(MO1.getReg()); in printAM3PreOrOffsetIndexOp()
444 if (MO2.getReg()) { in printAM3PreOrOffsetIndexOp()
446 << getRegisterName(MO2.getReg()) << ']'; in printAM3PreOrOffsetIndexOp()
485 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
487 << getRegisterName(MO1.getReg()); in printAddrMode3OffsetOperand()
510 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg()); in printPostIdxRegOperand()
539 O << "[" << getRegisterName(MO1.getReg()); in printAddrMode5Operand()
556 O << "[" << getRegisterName(MO1.getReg()); in printAddrMode6Operand()
567 O << "[" << getRegisterName(MO1.getReg()) << "]"; in printAddrMode7Operand()
574 if (MO.getReg() == 0) in printAddrMode6OffsetOperand()
577 O << ", " << getRegisterName(MO.getReg()); in printAddrMode6OffsetOperand()
632 O << getRegisterName(MI->getOperand(i).getReg()); in printRegisterList()
763 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand()
764 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && in printSBitModifierOperand()
852 O << "[" << getRegisterName(MO1.getReg()); in printThumbAddrModeRROperand()
853 if (unsigned RegNum = MO2.getReg()) in printThumbAddrModeRROperand()
870 O << "[" << getRegisterName(MO1.getReg()); in printThumbAddrModeImm5SOperand()
908 unsigned Reg = MO1.getReg(); in printT2SOOperand()
929 O << "[" << getRegisterName(MO1.getReg()); in printAddrModeImm12Operand()
949 O << "[" << getRegisterName(MO1.getReg()); in printT2AddrModeImm8Operand()
973 O << "[" << getRegisterName(MO1.getReg()); in printT2AddrModeImm8s4Operand()
995 O << "[" << getRegisterName(MO1.getReg()); in printT2AddrModeImm0_1020s4Operand()
1037 O << "[" << getRegisterName(MO1.getReg()); in printT2AddrModeSoRegOperand()
1039 assert(MO2.getReg() && "Invalid so_reg load / store address!"); in printT2AddrModeSoRegOperand()
1040 O << ", " << getRegisterName(MO2.getReg()); in printT2AddrModeSoRegOperand()
1102 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}"; in printVectorListOne()
1107 unsigned Reg = MI->getOperand(OpNum).getReg(); in printVectorListTwo()
1116 unsigned Reg = MI->getOperand(OpNum).getReg(); in printVectorListTwoSpaced()
1127 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " in printVectorListThree()
1128 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " in printVectorListThree()
1129 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; in printVectorListThree()
1137 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " in printVectorListFour()
1138 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " in printVectorListFour()
1139 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " in printVectorListFour()
1140 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}"; in printVectorListFour()
1146 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}"; in printVectorListOneAllLanes()
1152 unsigned Reg = MI->getOperand(OpNum).getReg(); in printVectorListTwoAllLanes()
1164 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " in printVectorListThreeAllLanes()
1165 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " in printVectorListThreeAllLanes()
1166 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}"; in printVectorListThreeAllLanes()
1175 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " in printVectorListFourAllLanes()
1176 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " in printVectorListFourAllLanes()
1177 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " in printVectorListFourAllLanes()
1178 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}"; in printVectorListFourAllLanes()
1184 unsigned Reg = MI->getOperand(OpNum).getReg(); in printVectorListTwoSpacedAllLanes()
1196 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " in printVectorListThreeSpacedAllLanes()
1197 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " in printVectorListThreeSpacedAllLanes()
1198 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}"; in printVectorListThreeSpacedAllLanes()
1207 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " in printVectorListFourSpacedAllLanes()
1208 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " in printVectorListFourSpacedAllLanes()
1209 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], " in printVectorListFourSpacedAllLanes()
1210 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}"; in printVectorListFourSpacedAllLanes()
1219 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " in printVectorListThreeSpaced()
1220 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " in printVectorListThreeSpaced()
1221 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}"; in printVectorListThreeSpaced()
1230 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " in printVectorListFourSpaced()
1231 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " in printVectorListFourSpaced()
1232 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", " in printVectorListFourSpaced()
1233 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}"; in printVectorListFourSpaced()