68                                       unsigned DestReg, unsigned SubIdx,  in emitLoadConstPool()  argument
79     .addReg(DestReg, getDefRegState(true), SubIdx)  in emitLoadConstPool()
93                               unsigned DestReg, unsigned BaseReg,  in emitThumbRegPlusImmInReg()  argument
99     bool isHigh = !isARMLowRegister(DestReg) ||  in emitThumbRegPlusImmInReg()
110     unsigned LdReg = DestReg;  in emitThumbRegPlusImmInReg()
111     if (DestReg == ARM::SP) {  in emitThumbRegPlusImmInReg()
131       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);  in emitThumbRegPlusImmInReg()
134     if (DestReg == ARM::SP || isSub)  in emitThumbRegPlusImmInReg()
170                                      unsigned DestReg, unsigned BaseReg,  in emitThumbRegPlusImmediate()  argument
186   if (DestReg == BaseReg && BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
208     if (DestReg != BaseReg)  in emitThumbRegPlusImmediate()
211     if (DestReg == ARM::SP) {  in emitThumbRegPlusImmediate()
225   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;  in emitThumbRegPlusImmediate()
230                              DestReg, BaseReg, NumBytes, true,  in emitThumbRegPlusImmediate()
236     if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {  in emitThumbRegPlusImmediate()
243         AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)  in emitThumbRegPlusImmediate()
247       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitThumbRegPlusImmediate()
251     BaseReg = DestReg;  in emitThumbRegPlusImmediate()
261       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);  in emitThumbRegPlusImmediate()
264       MIB.addReg(DestReg).addImm(ThisVal);  in emitThumbRegPlusImmediate()
269       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);  in emitThumbRegPlusImmediate()
276       BaseReg = DestReg;  in emitThumbRegPlusImmediate()
292     AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))  in emitThumbRegPlusImmediate()
293                    .addReg(DestReg, RegState::Kill)  in emitThumbRegPlusImmediate()
344                               unsigned DestReg, int Imm,  in emitThumbConstant()  argument
355                                         DestReg))  in emitThumbConstant()
358     emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI);  in emitThumbConstant()
361     AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))  in emitThumbConstant()
362                    .addReg(DestReg, RegState::Kill));  in emitThumbConstant()
441     unsigned DestReg = MI.getOperand(0).getReg();  in rewriteFrameIndex()  local
447       emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,  in rewriteFrameIndex()
468       emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,  in rewriteFrameIndex()
474       emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);  in rewriteFrameIndex()
477       MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);  in rewriteFrameIndex()