Lines Matching refs:two

16   // ALU instruction with one destination register and either two register
19   // two source operands are read during the decode stage and the result is
25                [ 2                    // result ready after two cycles
29   // ALU multiply instruction with one destination register and either two
33   // two source operands are read during the decode stage and the result is
43   // ALU divide instruction with one destination register two register source
45   // stages except the execute stage, which takes 34 cycles. The two
56   // Shift instruction with one destination register and either two register
59   // except the execute stage, which takes two cycles.  The two source operands
65                , InstrStage<2,[EX]>], // two cycles in execute stage
79   // Conditional branch instruction with two source operand registers. The
81   // two source operands are read during the decode stage.
97                [ 2                    // result ready after two cycles
100   // Cache control instruction with two source operand registers. The
102   // except the memory access stage, which takes two cycles. The source
107                , InstrStage<2,[EX]>], // two cycles in execute stage
111   // Floating point instruction with one destination register and two source
124   // Floating point divide instruction with one destination register and two
174   // two source operand registers. The instruction takes one cycle to execute
188   // of the pipeline stages except the execute stage, which takes two cycles.
194                , InstrStage<2,[EX]>], // two cycles in execute stage
195                [ 3                    // result ready after two cycles
198   // FSL put instruction with either two register source operands or one
201   // each of the pipeline stages except the execute stage, which takes two
202   // cycles. The two source operands are read during the decode stage.
206                , InstrStage<2,[EX]>], // two cycles in execute stage
210   // Memory store instruction with either three register source operands or two
213   // each of the pipeline stages except the execute stage, which takes two
218                , InstrStage<2,[EX]>], // two cycles in execute stage
223   // Memory load instruction with one destination register and either two
226   // pipeline stages except the execute stage, which takes two cycles. All of
232                , InstrStage<2,[EX]>], // two cycles in execute stage