Lines Matching refs:MCOperand
334 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeCPU64RegsRegisterClass()
345 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeCPURegsRegisterClass()
357 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFGR64RegisterClass()
369 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFGR32RegisterClass()
377 Inst.addOperand(MCOperand::CreateReg(RegNo)); in DecodeCCRRegisterClass()
393 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeMem()
396 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeMem()
397 Inst.addOperand(MCOperand::CreateReg(Base)); in DecodeMem()
398 Inst.addOperand(MCOperand::CreateImm(Offset)); in DecodeMem()
414 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFMem()
415 Inst.addOperand(MCOperand::CreateReg(Base)); in DecodeFMem()
416 Inst.addOperand(MCOperand::CreateImm(Offset)); in DecodeFMem()
429 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); in DecodeHWRegsRegisterClass()
438 Inst.addOperand(MCOperand::CreateImm(CondCode)); in DecodeCondCode()
451 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeAFGR64RegisterClass()
462 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); in DecodeHWRegs64RegisterClass()
472 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); in DecodeBranchTarget()
482 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); in DecodeBC1()
492 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); in DecodeJumpTarget()
501 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); in DecodeSimm16()
512 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); in DecodeInsSize()
521 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); in DecodeExtSize()