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Lines Matching refs:Fixups

59                          SmallVectorImpl<MCFixup> &Fixups) const;
64 SmallVectorImpl<MCFixup> &Fixups) const;
70 SmallVectorImpl<MCFixup> &Fixups) const;
76 SmallVectorImpl<MCFixup> &Fixups) const;
81 SmallVectorImpl<MCFixup> &Fixups) const;
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 SmallVectorImpl<MCFixup> &Fixups) const;
113 SmallVectorImpl<MCFixup> &Fixups) const in EncodeInstruction()
115 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); in EncodeInstruction()
143 SmallVectorImpl<MCFixup> &Fixups) const { in getBranchTargetOpValue()
153 Fixups.push_back(MCFixup::Create(0, Expr, in getBranchTargetOpValue()
163 SmallVectorImpl<MCFixup> &Fixups) const { in getJumpTargetOpValue()
172 Fixups.push_back(MCFixup::Create(0, Expr, in getJumpTargetOpValue()
181 SmallVectorImpl<MCFixup> &Fixups) const { in getMachineOpValue()
206 Mips::Fixups FixupKind = Mips::Fixups(0); in getMachineOpValue()
273 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind))); in getMachineOpValue()
283 SmallVectorImpl<MCFixup> &Fixups) const { in getMemEncoding()
286 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; in getMemEncoding()
287 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); in getMemEncoding()
294 SmallVectorImpl<MCFixup> &Fixups) const { in getSizeExtEncoding()
296 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); in getSizeExtEncoding()
304 SmallVectorImpl<MCFixup> &Fixups) const { in getSizeInsEncoding()
307 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups); in getSizeInsEncoding()
308 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); in getSizeInsEncoding()