Lines Matching refs:ry
19 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
20 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
59 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
60 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
65 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
66 !strconcat(asmstr, "\t$rz, $ry"),
83 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
84 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
88 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
89 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
95 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
96 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
137 // Format: ADDU rz, rx, ry MIPS16e
145 // Format: AND rx, ry MIPS16e
161 // Format: LB ry, offset(rx) MIPS16e
168 // Format: LBU ry, offset(rx) MIPS16e
175 // Format: LH ry, offset(rx) MIPS16e
182 // Format: LHU ry, offset(rx) MIPS16e
196 // Format: LW ry, offset(rx) MIPS16e
210 // Format: NEG rx, ry MIPS16e
217 // Format: NOT rx, ry MIPS16e
224 // Format: OR rx, ry MIPS16e
261 // Format: SB ry, offset(rx) MIPS16e
268 // Format: SH ry, offset(rx) MIPS16e
275 // Format: SLL rx, ry, sa MIPS16e
282 // Format: SLLV ry, rx MIPS16e
290 // Format: SRAV ry, rx MIPS16e
299 // Format: SRA rx, ry, sa MIPS16e
308 // Format: SRLV ry, rx MIPS16e
317 // Format: SRL rx, ry, sa MIPS16e
325 // Format: SUBU rz, rx, ry MIPS16e
332 // Format: SW ry, offset(rx) MIPS16e
339 // Format: XOR rx, ry MIPS16e