Lines Matching refs:SRL
653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) in PerformANDCombine()
1845 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in LowerFCOPYSIGN32()
1846 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in LowerFCOPYSIGN32()
1892 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in LowerFCOPYSIGN64()
1893 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in LowerFCOPYSIGN64()
1933 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in LowerFABS32()
1958 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in LowerFABS64()
2037 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, in LowerShiftLeftParts()
2039 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, in LowerShiftLeftParts()
2078 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); in LowerShiftRightParts()
2080 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, in LowerShiftRightParts()
2169 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in LowerLOAD() local
2170 SDValue Ops[] = { SRL, LWR.getValue(1) }; in LowerLOAD()