87                                   unsigned DestReg, unsigned SrcReg,  in copyPhysReg()  argument
91   if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.  in copyPhysReg()
104     if (Mips::CCRRegClass.contains(DestReg))  in copyPhysReg()
106     else if (Mips::FGR32RegClass.contains(DestReg))  in copyPhysReg()
108     else if (DestReg == Mips::HI)  in copyPhysReg()
109       Opc = Mips::MTHI, DestReg = 0;  in copyPhysReg()
110     else if (DestReg == Mips::LO)  in copyPhysReg()
111       Opc = Mips::MTLO, DestReg = 0;  in copyPhysReg()
113   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
115   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
117   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
119   else if (Mips::CCRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
121   else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.  in copyPhysReg()
132     if (DestReg == Mips::HI64)  in copyPhysReg()
133       Opc = Mips::MTHI64, DestReg = 0;  in copyPhysReg()
134     else if (DestReg == Mips::LO64)  in copyPhysReg()
135       Opc = Mips::MTLO64, DestReg = 0;  in copyPhysReg()
136     else if (Mips::FGR64RegClass.contains(DestReg))  in copyPhysReg()
144   if (DestReg)  in copyPhysReg()
145     MIB.addReg(DestReg, RegState::Define);  in copyPhysReg()
183                      unsigned DestReg, int FI,  in loadRegFromStackSlot()  argument
204   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()