Lines Matching refs:CONCAT_VECTORS

1152       setOperationAction(ISD::CONCAT_VECTORS,     VT, Custom);  in X86TargetLowering()
4465     V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);  in PromoteSplat()
6261   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);  in LowerVECTOR_SHUFFLE_256()
8749   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,  in Lower256IntVSETCC()
10618   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,  in Lower256IntArith()
10906     return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);  in LowerShift()
11027         return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);  in LowerSIGN_EXTEND_INREG()
11274   case ISD::CONCAT_VECTORS:     return LowerCONCAT_VECTORS(Op, DAG);  in LowerOperation()
13397   if (V1.getOpcode() == ISD::CONCAT_VECTORS &&  in PerformShuffleCombine256()
13398       V2.getOpcode() == ISD::CONCAT_VECTORS) {  in PerformShuffleCombine256()
15202       StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&  in PerformSTORECombine()
15702     return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);  in PerformSExtCombine()
15808     return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);  in PerformZExtCombine()