4457   EVT EltVT = SrcVT.getVectorElementType();  in PromoteSplat()  local
4458   if (EltVT == MVT::i8 || EltVT == MVT::i16)  in PromoteSplat()
4944   EVT EltVT = VT.getVectorElementType();  in EltsFromConsecutiveLoads()  local
4970     if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))  in EltsFromConsecutiveLoads()
6165   MVT EltVT = VT.getVectorElementType().getSimpleVT();  in LowerVECTOR_SHUFFLE_256()  local
6166   EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);  in LowerVECTOR_SHUFFLE_256()
6223           SVOps.push_back(DAG.getUNDEF(EltVT));  in LowerVECTOR_SHUFFLE_256()
6234         SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,  in LowerVECTOR_SHUFFLE_256()
6697     EVT EltVT = VT.getVectorElementType();  in LowerVECTOR_SHUFFLE()  local
6698     ShAmt *= EltVT.getSizeInBits();  in LowerVECTOR_SHUFFLE()
6736     EVT EltVT = VT.getVectorElementType();  in LowerVECTOR_SHUFFLE()  local
6737     ShAmt *= EltVT.getSizeInBits();  in LowerVECTOR_SHUFFLE()
7029     EVT EltVT = MVT::i32;  in LowerEXTRACT_VECTOR_ELT()  local
7030     SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,  in LowerEXTRACT_VECTOR_ELT()
7032     SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,  in LowerEXTRACT_VECTOR_ELT()
7077   EVT EltVT = VT.getVectorElementType();  in LowerINSERT_VECTOR_ELT_SSE4()  local
7087   if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&  in LowerINSERT_VECTOR_ELT_SSE4()
7106   if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {  in LowerINSERT_VECTOR_ELT_SSE4()
7121   if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {  in LowerINSERT_VECTOR_ELT_SSE4()
7131   EVT EltVT = VT.getVectorElementType();  in LowerINSERT_VECTOR_ELT()  local
7161   if (EltVT == MVT::i8)  in LowerINSERT_VECTOR_ELT()
7164   if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {  in LowerINSERT_VECTOR_ELT()
8206   EVT EltVT = VT;  in LowerFABS()  local
8209     EltVT = VT.getVectorElementType();  in LowerFABS()
8213   if (EltVT == MVT::f64)  in LowerFABS()
8238   EVT EltVT = VT;  in LowerFNEG()  local
8241     EltVT = VT.getVectorElementType();  in LowerFNEG()
8245   if (EltVT == MVT::f64)  in LowerFNEG()
8747   MVT EltVT = VT.getVectorElementType().getSimpleVT();  in Lower256IntVSETCC()  local
8748   EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);  in Lower256IntVSETCC()
8767     EVT EltVT = Op0.getValueType().getVectorElementType();  in LowerVSETCC()  local
8768     assert(EltVT == MVT::f32 || EltVT == MVT::f64);  in LowerVSETCC()
8869     EVT EltVT = VT.getVectorElementType();  in LowerVSETCC()  local
8870     SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),  in LowerVSETCC()
8871                                       EltVT);  in LowerVSETCC()
9644   MVT EltVT = VT.getVectorElementType().getSimpleVT();  in getTargetVShiftNode()  local
9645   EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());  in getTargetVShiftNode()
10615   MVT EltVT = VT.getVectorElementType().getSimpleVT();  in Lower256IntArith()  local
10616   EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);  in Lower256IntArith()
10873     MVT EltVT = VT.getVectorElementType().getSimpleVT();  in LowerShift()  local
10874     EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);  in LowerShift()
11015         MVT EltVT = VT.getVectorElementType().getSimpleVT();  in LowerSIGN_EXTEND_INREG()  local
11016         EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);  in LowerSIGN_EXTEND_INREG()
14561   EVT EltVT = VT.getVectorElementType();  in PerformShiftCombine()  local
14607       if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&  in PerformShiftCombine()
14611       BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,  in PerformShiftCombine()
14618   if (EltVT.bitsGT(MVT::i32))  in PerformShiftCombine()
14620   else if (EltVT.bitsLT(MVT::i32))  in PerformShiftCombine()