755     setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);  in X86TargetLowering()
986     setOperationAction(ISD::SRL,               MVT::v8i16, Custom);  in X86TargetLowering()
987     setOperationAction(ISD::SRL,               MVT::v16i8, Custom);  in X86TargetLowering()
996       setOperationAction(ISD::SRL,             MVT::v2i64, Legal);  in X86TargetLowering()
997       setOperationAction(ISD::SRL,             MVT::v4i32, Legal);  in X86TargetLowering()
1004       setOperationAction(ISD::SRL,             MVT::v2i64, Custom);  in X86TargetLowering()
1005       setOperationAction(ISD::SRL,             MVT::v4i32, Custom);  in X86TargetLowering()
1050     setOperationAction(ISD::SRL,               MVT::v16i16, Custom);  in X86TargetLowering()
1051     setOperationAction(ISD::SRL,               MVT::v32i8, Custom);  in X86TargetLowering()
1100       setOperationAction(ISD::SRL,             MVT::v4i64, Legal);  in X86TargetLowering()
1101       setOperationAction(ISD::SRL,             MVT::v8i32, Legal);  in X86TargetLowering()
1123       setOperationAction(ISD::SRL,             MVT::v4i64, Custom);  in X86TargetLowering()
1124       setOperationAction(ISD::SRL,             MVT::v8i32, Custom);  in X86TargetLowering()
1224   setTargetDAGCombine(ISD::SRL);  in X86TargetLowering()
6013         InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,  in LowerVECTOR_SHUFFLEv16i8()
7755     Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);  in LowerShiftParts()
8592   SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,  in ConvertCmpIfNecessary()
8633     if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {  in LowerToBT()
9837       Opcode = ISD::SRL;  in LowerINTRINSIC_WO_CHAIN()
10492     DAG.getNode(ISD::SRL, DL, MVT::i16,  in LowerFLT_ROUNDS_()
10497     DAG.getNode(ISD::SRL, DL, MVT::i16,  in LowerFLT_ROUNDS_()
10709         if (Op.getOpcode() == ISD::SRL)  in LowerShift()
10730         if (Op.getOpcode() == ISD::SRL) {  in LowerShift()
10732           SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,  in LowerShift()  local
10734           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);  in LowerShift()
10739           return DAG.getNode(ISD::AND, dl, VT, SRL,  in LowerShift()
10750           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);  in LowerShift()
10774         if (Op.getOpcode() == ISD::SRL) {  in LowerShift()
10776           SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,  in LowerShift()  local
10778           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);  in LowerShift()
10783           return DAG.getNode(ISD::AND, dl, VT, SRL,  in LowerShift()
10794           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);  in LowerShift()
11320   case ISD::SRL:  in LowerOperation()
14648   case ISD::SRL:  in PerformShiftCombine()
14940   if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)  in PerformOrCombine()
14942   if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)  in PerformOrCombine()
16096   case ISD::SRL:            return PerformShiftCombine(N, DAG, DCI, Subtarget);  in PerformDAGCombine()
16159   case ISD::SRL:  in isTypeDesirableForOp()
16205   case ISD::SRL: {  in IsDesirableToPromoteOp()