Lines Matching refs:OpSize
806 TB, OpSize, VEX;
812 TB, OpSize, VEX;
819 TB, OpSize, VEX;
825 TB, OpSize, VEX;
831 TB, OpSize;
837 TB, OpSize;
1151 itin, SSEPackedDouble>, TB, OpSize;
2005 // SSE2 instructions without OpSize prefix
2254 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2261 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2268 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2273 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2277 "ucomisd", SSEPackedDouble>, TB, OpSize;
2283 "comisd", SSEPackedDouble>, TB, OpSize;
2289 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2294 "comisd", SSEPackedDouble>, TB, OpSize;
2328 SSEPackedDouble>, TB, OpSize, VEX_4V;
2336 SSEPackedDouble>, TB, OpSize, VEX_4V;
2345 SSEPackedDouble>, TB, OpSize;
2409 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2412 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2422 TB, OpSize;
2496 SSEPackedDouble>, TB, OpSize, VEX_4V;
2502 SSEPackedDouble>, TB, OpSize, VEX_4V;
2509 SSEPackedDouble>, TB, OpSize, VEX_4V;
2515 SSEPackedDouble>, TB, OpSize, VEX_4V;
2523 SSEPackedDouble>, TB, OpSize;
2529 SSEPackedDouble>, TB, OpSize;
2590 OpSize, VEX;
2595 OpSize, VEX;
2613 OpSize, VEX;
2620 OpSize, VEX;
2626 SSEPackedDouble>, TB, OpSize;
2721 TB, OpSize, VEX_4V;
2730 TB, OpSize;
2765 TB, OpSize, VEX_4V;
2778 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2798 TB, OpSize, VEX_4V;
2849 TB, OpSize;
2860 TB, OpSize;
2885 TB, OpSize;
2896 SSEPackedDouble, itins.d, 0>, TB, OpSize;
4235 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4250 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4257 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4401 imm:$src2))]>, TB, OpSize, VEX;
4410 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4414 []>, TB, OpSize, VEX_4V;
4418 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4583 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
5059 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5061 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5070 f128mem, SSE_ALU_F64P>, TB, OpSize;
5155 OpSize;
5163 OpSize;
5173 OpSize;
5180 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5243 OpSize;
5251 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5265 OpSize;
5273 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5283 OpSize;
5289 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5415 [], IIC_SSE_PALIGNR>, OpSize;
5423 [], IIC_SSE_PALIGNR>, OpSize;
5433 []>, OpSize;
5439 []>, OpSize;
5516 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5522 OpSize;
5529 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5533 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5665 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5671 OpSize;
5678 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5684 OpSize;
5743 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5750 OpSize;
5757 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5764 OpSize;
5819 OpSize;
5825 []>, OpSize;
5835 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5848 []>, OpSize;
5867 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5873 addr:$dst)]>, OpSize;
5888 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5894 addr:$dst)]>, OpSize, REX_W;
5911 OpSize;
5917 addr:$dst)]>, OpSize;
5926 []>, OpSize, VEX;
5955 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5964 imm:$src3))]>, OpSize;
5981 OpSize;
5990 imm:$src3)))]>, OpSize;
6007 OpSize;
6016 imm:$src3)))]>, OpSize;
6037 OpSize;
6047 imm:$src3))]>, OpSize;
6073 OpSize;
6082 OpSize;
6092 OpSize;
6101 OpSize;
6118 []>, OpSize;
6129 OpSize;
6141 OpSize;
6151 []>, OpSize;
6162 OpSize;
6174 OpSize;
6269 OpSize, VEX;
6273 OpSize, VEX;
6278 OpSize, VEX;
6282 OpSize, VEX;
6289 OpSize;
6293 OpSize;
6301 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6305 OpSize, VEX;
6327 OpSize, XS;
6331 (implicit EFLAGS)]>, OpSize, XS;
6360 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6366 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6384 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6392 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6402 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6408 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6483 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6491 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6527 OpSize;
6538 OpSize;
6610 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6619 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6709 OpSize;
6717 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6777 OpSize, VEX;
6782 OpSize, VEX;
6786 OpSize;
6802 OpSize;
6809 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6848 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6852 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6858 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6862 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6886 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6890 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6896 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6900 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6909 []>, OpSize;
6914 []>, OpSize;
6928 []>, OpSize;
6933 []>, OpSize;
6968 OpSize;
6974 OpSize;
7026 OpSize;
7033 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7066 OpSize, VEX;
7071 OpSize, VEX;
7078 OpSize;
7083 OpSize;
7092 OpSize, VEX;
7098 OpSize, VEX;
7105 OpSize;
7111 OpSize;
7177 imm:$idx))]>, TB, OpSize;
7182 VR128:$mask))]>, TB, OpSize;
7569 T8, OpSize, VEX;
7572 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7580 TA, OpSize, VEX;
7585 TA, OpSize, VEX;