94 static cache_t2 I1, D1, LL;  variable
308     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in cachesim_I1_ref()
316     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in cachesim_D1_ref()
415     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in cachesim_I1_Read()
427     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in cachesim_D1_Read()
443 	cachesim_ref_wb( &LL, Write, a, size);  in cachesim_D1_Write()
446     switch( cachesim_ref_wb( &LL, Write, a, size) ) {  in cachesim_D1_Write()
485   UInt block = ( a >> LL.line_size_bits);  in prefetch_LL_doref()
497 	  cachesim_ref(&LL, a + 5 * LL.line_size,1);  in prefetch_LL_doref()
507 	  cachesim_ref(&LL, a - 5 * LL.line_size,1);  in prefetch_LL_doref()
523     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in prefetch_I1_ref()
532     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in prefetch_D1_ref()
544     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in prefetch_I1_Read()
557     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in prefetch_D1_Read()
574 	cachesim_ref_wb( &LL, Write, a, size);  in prefetch_D1_Write()
577     switch( cachesim_ref_wb( &LL, Write, a, size) ) {  in prefetch_D1_Write()
842   line_loaded* loaded = &(LL.loaded[idx]);  in update_LL_use()
843   line_use* use = &(LL.use[idx]);  in update_LL_use()
844   int i = ((32 - countBits(use->mask)) * LL.line_size)>>5;  in update_LL_use()
873    UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);  in cacheuse_LL_access()
874    UWord* set = &(LL.tags[setNo * LL.assoc]);  in cacheuse_LL_access()
875    UWord tag  = memline & LL.tag_mask;  in cacheuse_LL_access()
882    if (tag == (set[0] & LL.tag_mask)) {  in cacheuse_LL_access()
883      idx = (setNo * LL.assoc) + (set[0] & ~LL.tag_mask);  in cacheuse_LL_access()
884      l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
887 		 idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
888 		 LL.use[idx].mask, LL.use[idx].count);  in cacheuse_LL_access()
891    for (i = 1; i < LL.assoc; i++) {  in cacheuse_LL_access()
892      if (tag == (set[i] & LL.tag_mask)) {  in cacheuse_LL_access()
898        idx = (setNo * LL.assoc) + (tmp_tag & ~LL.tag_mask);  in cacheuse_LL_access()
899        l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
902 		 i, idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
903 		 LL.use[idx].mask, LL.use[idx].count);  in cacheuse_LL_access()
909    tmp_tag = set[LL.assoc - 1] & ~LL.tag_mask;  in cacheuse_LL_access()
910    for (j = LL.assoc - 1; j > 0; j--) {  in cacheuse_LL_access()
914    idx = (setNo * LL.assoc) + tmp_tag;  in cacheuse_LL_access()
915    l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
994   if (LL.use)  in cacheuse_finish()
995     for (i = 0; i < LL.sets * LL.assoc; i++)  in cacheuse_finish()
996       if (LL.loaded[i].use_base)  in cacheuse_finish()
1308   LL.name = "LL";  in cachesim_post_clo_init()
1312   cachesim_initcache(LLc, &LL);  in cachesim_post_clo_init()
1393   cachesim_clearcache(&LL);  in cachesim_clear()
1404   VG_(sprintf)(buf+p, "desc: LL cache: %s\n", LL.desc_line);  in cachesim_getdesc()