1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMInstrInfo.h" 15 #include "ARM.h" 16 #include "ARMMachineFunctionInfo.h" 17 #include "MCTargetDesc/ARMAddressingModes.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/CodeGen/LiveVariables.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCInst.h" 25 using namespace llvm; 26 ARMInstrInfo(const ARMSubtarget & STI)27ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) 28 : ARMBaseInstrInfo(STI), RI(*this, STI) { 29 } 30 31 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. getNoopForMachoTarget(MCInst & NopInst) const32void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 33 if (hasNOP()) { 34 NopInst.setOpcode(ARM::HINT); 35 NopInst.addOperand(MCOperand::CreateImm(0)); 36 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 37 NopInst.addOperand(MCOperand::CreateReg(0)); 38 } else { 39 NopInst.setOpcode(ARM::MOVr); 40 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 41 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 42 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 43 NopInst.addOperand(MCOperand::CreateReg(0)); 44 NopInst.addOperand(MCOperand::CreateReg(0)); 45 } 46 } 47 getUnindexedOpcode(unsigned Opc) const48unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { 49 switch (Opc) { 50 default: break; 51 case ARM::LDR_PRE_IMM: 52 case ARM::LDR_PRE_REG: 53 case ARM::LDR_POST_IMM: 54 case ARM::LDR_POST_REG: 55 return ARM::LDRi12; 56 case ARM::LDRH_PRE: 57 case ARM::LDRH_POST: 58 return ARM::LDRH; 59 case ARM::LDRB_PRE_IMM: 60 case ARM::LDRB_PRE_REG: 61 case ARM::LDRB_POST_IMM: 62 case ARM::LDRB_POST_REG: 63 return ARM::LDRBi12; 64 case ARM::LDRSH_PRE: 65 case ARM::LDRSH_POST: 66 return ARM::LDRSH; 67 case ARM::LDRSB_PRE: 68 case ARM::LDRSB_POST: 69 return ARM::LDRSB; 70 case ARM::STR_PRE_IMM: 71 case ARM::STR_PRE_REG: 72 case ARM::STR_POST_IMM: 73 case ARM::STR_POST_REG: 74 return ARM::STRi12; 75 case ARM::STRH_PRE: 76 case ARM::STRH_POST: 77 return ARM::STRH; 78 case ARM::STRB_PRE_IMM: 79 case ARM::STRB_PRE_REG: 80 case ARM::STRB_POST_IMM: 81 case ARM::STRB_POST_REG: 82 return ARM::STRBi12; 83 } 84 85 return 0; 86 } 87