| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
306 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
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| /external/llvm/include/llvm/Transforms/Utils/ |
| D | AddrModeMatcher.h | 37 Value *BaseReg; member
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 138 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 129 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
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| /external/llvm/lib/Target/X86/ |
| D | X86CodeEmitter.cpp | 481 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
612 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
626 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
641 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
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| D | X86AsmPrinter.cpp | 312 const MachineOperand &BaseReg = MI->getOperand(Op); in printLeaMemReference() local
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| D | X86InstrInfo.cpp | 1500 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { in regIsPICBase()
1553 unsigned BaseReg = MI->getOperand(1).getReg(); in isReallyTriviallyReMaterializable() local
1574 unsigned BaseReg = MI->getOperand(1).getReg(); in isReallyTriviallyReMaterializable() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1RegisterInfo.cpp | 93 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg()
170 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate()
532 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| D | Thumb2SizeReduction.cpp | 380 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
402 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
416 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| D | ARMBaseRegisterInfo.cpp | 942 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
967 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| D | Thumb2InstrInfo.cpp | 179 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate()
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| D | ARMLoadStoreOptimizer.cpp | 1077 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR()
1103 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1563 unsigned &OddReg, unsigned &BaseReg, in CanFormLdStDWord()
1725 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
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| D | ARMISelDAGToDAG.cpp | 386 SDValue &BaseReg, in SelectImmShifterOperand()
409 SDValue &BaseReg, in SelectRegShifterOperand()
1147 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, in SelectT2ShifterOperandReg()
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| D | ARMBaseInstrInfo.cpp | 154 unsigned BaseReg = Base.getReg(); in convertToThreeAddress() local
1737 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate()
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| D | ARMConstantIslandPass.cpp | 1879 unsigned BaseReg = MI->getOperand(0).getReg(); in optimizeThumb2JumpTables() local
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| /external/llvm/lib/Transforms/Utils/ |
| D | AddrModeMatcher.cpp | 518 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in IsProfitableToFoldIntoAddressingMode() local
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 697 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
706 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 191 unsigned BaseReg; member
649 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseIntelBracExpression() local
885 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 911 const SCEV *BaseReg = *I; in RateFormula() local
3089 const SCEV *BaseReg = Base.BaseRegs[i]; in GenerateReassociations() local
3174 const SCEV *BaseReg = *I; in GenerateCombinations() local
3582 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 192 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst() local
|