1 #if !defined (__MIPS_CPU_H__)
2 #define __MIPS_CPU_H__
3
4 #define TARGET_HAS_ICE 1
5
6 #define ELF_MACHINE EM_MIPS
7
8 #define CPUState struct CPUMIPSState
9
10 #include "config.h"
11 #include "mips-defs.h"
12 #include "cpu-defs.h"
13 #include "softfloat.h"
14
15 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
16 // XXX: move that elsewhere
17 #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
18 typedef unsigned char uint_fast8_t;
19 typedef unsigned int uint_fast16_t;
20 #endif
21
22 struct CPUMIPSState;
23
24 typedef struct r4k_tlb_t r4k_tlb_t;
25 struct r4k_tlb_t {
26 target_ulong VPN;
27 uint32_t PageMask;
28 uint_fast8_t ASID;
29 uint_fast16_t G:1;
30 uint_fast16_t C0:3;
31 uint_fast16_t C1:3;
32 uint_fast16_t V0:1;
33 uint_fast16_t V1:1;
34 uint_fast16_t D0:1;
35 uint_fast16_t D1:1;
36 target_ulong PFN[2];
37 };
38
39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
40 struct CPUMIPSTLBContext {
41 uint32_t nb_tlb;
42 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
43 void (*helper_tlbwi) (void);
44 void (*helper_tlbwr) (void);
45 void (*helper_tlbp) (void);
46 void (*helper_tlbr) (void);
47 union {
48 struct {
49 r4k_tlb_t tlb[MIPS_TLB_MAX];
50 } r4k;
51 } mmu;
52 };
53
54 typedef union fpr_t fpr_t;
55 union fpr_t {
56 float64 fd; /* ieee double precision */
57 float32 fs[2];/* ieee single precision */
58 uint64_t d; /* binary double fixed-point */
59 uint32_t w[2]; /* binary single fixed-point */
60 };
61 /* define FP_ENDIAN_IDX to access the same location
62 * in the fpr_t union regardless of the host endianess
63 */
64 #if defined(HOST_WORDS_BIGENDIAN)
65 # define FP_ENDIAN_IDX 1
66 #else
67 # define FP_ENDIAN_IDX 0
68 #endif
69
70 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
71 struct CPUMIPSFPUContext {
72 /* Floating point registers */
73 fpr_t fpr[32];
74 float_status fp_status;
75 /* fpu implementation/revision register (fir) */
76 uint32_t fcr0;
77 #define FCR0_F64 22
78 #define FCR0_L 21
79 #define FCR0_W 20
80 #define FCR0_3D 19
81 #define FCR0_PS 18
82 #define FCR0_D 17
83 #define FCR0_S 16
84 #define FCR0_PRID 8
85 #define FCR0_REV 0
86 /* fcsr */
87 uint32_t fcr31;
88 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
90 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
91 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
92 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
93 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
94 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
95 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
96 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
97 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
98 #define FP_INEXACT 1
99 #define FP_UNDERFLOW 2
100 #define FP_OVERFLOW 4
101 #define FP_DIV0 8
102 #define FP_INVALID 16
103 #define FP_UNIMPLEMENTED 32
104 };
105
106 #define NB_MMU_MODES 3
107
108 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
109 struct CPUMIPSMVPContext {
110 int32_t CP0_MVPControl;
111 #define CP0MVPCo_CPA 3
112 #define CP0MVPCo_STLB 2
113 #define CP0MVPCo_VPC 1
114 #define CP0MVPCo_EVP 0
115 int32_t CP0_MVPConf0;
116 #define CP0MVPC0_M 31
117 #define CP0MVPC0_TLBS 29
118 #define CP0MVPC0_GS 28
119 #define CP0MVPC0_PCP 27
120 #define CP0MVPC0_PTLBE 16
121 #define CP0MVPC0_TCA 15
122 #define CP0MVPC0_PVPE 10
123 #define CP0MVPC0_PTC 0
124 int32_t CP0_MVPConf1;
125 #define CP0MVPC1_CIM 31
126 #define CP0MVPC1_CIF 30
127 #define CP0MVPC1_PCX 20
128 #define CP0MVPC1_PCP2 10
129 #define CP0MVPC1_PCP1 0
130 };
131
132 typedef struct mips_def_t mips_def_t;
133
134 #define MIPS_SHADOW_SET_MAX 16
135 #define MIPS_TC_MAX 5
136 #define MIPS_FPU_MAX 1
137 #define MIPS_DSP_ACC 4
138
139 typedef struct TCState TCState;
140 struct TCState {
141 target_ulong gpr[32];
142 target_ulong PC;
143 target_ulong HI[MIPS_DSP_ACC];
144 target_ulong LO[MIPS_DSP_ACC];
145 target_ulong ACX[MIPS_DSP_ACC];
146 target_ulong DSPControl;
147 int32_t CP0_TCStatus;
148 #define CP0TCSt_TCU3 31
149 #define CP0TCSt_TCU2 30
150 #define CP0TCSt_TCU1 29
151 #define CP0TCSt_TCU0 28
152 #define CP0TCSt_TMX 27
153 #define CP0TCSt_RNST 23
154 #define CP0TCSt_TDS 21
155 #define CP0TCSt_DT 20
156 #define CP0TCSt_DA 15
157 #define CP0TCSt_A 13
158 #define CP0TCSt_TKSU 11
159 #define CP0TCSt_IXMT 10
160 #define CP0TCSt_TASID 0
161 int32_t CP0_TCBind;
162 #define CP0TCBd_CurTC 21
163 #define CP0TCBd_TBE 17
164 #define CP0TCBd_CurVPE 0
165 target_ulong CP0_TCHalt;
166 target_ulong CP0_TCContext;
167 target_ulong CP0_TCSchedule;
168 target_ulong CP0_TCScheFBack;
169 int32_t CP0_Debug_tcstatus;
170 };
171
172 typedef struct CPUMIPSState CPUMIPSState;
173 struct CPUMIPSState {
174 TCState active_tc;
175 CPUMIPSFPUContext active_fpu;
176
177 uint32_t current_tc;
178 uint32_t current_fpu;
179
180 uint32_t SEGBITS;
181 uint32_t PABITS;
182 target_ulong SEGMask;
183 target_ulong PAMask;
184
185 int32_t CP0_Index;
186 /* CP0_MVP* are per MVP registers. */
187 int32_t CP0_Random;
188 int32_t CP0_VPEControl;
189 #define CP0VPECo_YSI 21
190 #define CP0VPECo_GSI 20
191 #define CP0VPECo_EXCPT 16
192 #define CP0VPECo_TE 15
193 #define CP0VPECo_TargTC 0
194 int32_t CP0_VPEConf0;
195 #define CP0VPEC0_M 31
196 #define CP0VPEC0_XTC 21
197 #define CP0VPEC0_TCS 19
198 #define CP0VPEC0_SCS 18
199 #define CP0VPEC0_DSC 17
200 #define CP0VPEC0_ICS 16
201 #define CP0VPEC0_MVP 1
202 #define CP0VPEC0_VPA 0
203 int32_t CP0_VPEConf1;
204 #define CP0VPEC1_NCX 20
205 #define CP0VPEC1_NCP2 10
206 #define CP0VPEC1_NCP1 0
207 target_ulong CP0_YQMask;
208 target_ulong CP0_VPESchedule;
209 target_ulong CP0_VPEScheFBack;
210 int32_t CP0_VPEOpt;
211 #define CP0VPEOpt_IWX7 15
212 #define CP0VPEOpt_IWX6 14
213 #define CP0VPEOpt_IWX5 13
214 #define CP0VPEOpt_IWX4 12
215 #define CP0VPEOpt_IWX3 11
216 #define CP0VPEOpt_IWX2 10
217 #define CP0VPEOpt_IWX1 9
218 #define CP0VPEOpt_IWX0 8
219 #define CP0VPEOpt_DWX7 7
220 #define CP0VPEOpt_DWX6 6
221 #define CP0VPEOpt_DWX5 5
222 #define CP0VPEOpt_DWX4 4
223 #define CP0VPEOpt_DWX3 3
224 #define CP0VPEOpt_DWX2 2
225 #define CP0VPEOpt_DWX1 1
226 #define CP0VPEOpt_DWX0 0
227 target_ulong CP0_EntryLo0;
228 target_ulong CP0_EntryLo1;
229 target_ulong CP0_Context;
230 int32_t CP0_PageMask;
231 int32_t CP0_PageGrain;
232 int32_t CP0_Wired;
233 int32_t CP0_SRSConf0_rw_bitmask;
234 int32_t CP0_SRSConf0;
235 #define CP0SRSC0_M 31
236 #define CP0SRSC0_SRS3 20
237 #define CP0SRSC0_SRS2 10
238 #define CP0SRSC0_SRS1 0
239 int32_t CP0_SRSConf1_rw_bitmask;
240 int32_t CP0_SRSConf1;
241 #define CP0SRSC1_M 31
242 #define CP0SRSC1_SRS6 20
243 #define CP0SRSC1_SRS5 10
244 #define CP0SRSC1_SRS4 0
245 int32_t CP0_SRSConf2_rw_bitmask;
246 int32_t CP0_SRSConf2;
247 #define CP0SRSC2_M 31
248 #define CP0SRSC2_SRS9 20
249 #define CP0SRSC2_SRS8 10
250 #define CP0SRSC2_SRS7 0
251 int32_t CP0_SRSConf3_rw_bitmask;
252 int32_t CP0_SRSConf3;
253 #define CP0SRSC3_M 31
254 #define CP0SRSC3_SRS12 20
255 #define CP0SRSC3_SRS11 10
256 #define CP0SRSC3_SRS10 0
257 int32_t CP0_SRSConf4_rw_bitmask;
258 int32_t CP0_SRSConf4;
259 #define CP0SRSC4_SRS15 20
260 #define CP0SRSC4_SRS14 10
261 #define CP0SRSC4_SRS13 0
262 int32_t CP0_HWREna;
263 target_ulong CP0_BadVAddr;
264 int32_t CP0_Count;
265 target_ulong CP0_EntryHi;
266 int32_t CP0_Compare;
267 int32_t CP0_Status;
268 #define CP0St_CU3 31
269 #define CP0St_CU2 30
270 #define CP0St_CU1 29
271 #define CP0St_CU0 28
272 #define CP0St_RP 27
273 #define CP0St_FR 26
274 #define CP0St_RE 25
275 #define CP0St_MX 24
276 #define CP0St_PX 23
277 #define CP0St_BEV 22
278 #define CP0St_TS 21
279 #define CP0St_SR 20
280 #define CP0St_NMI 19
281 #define CP0St_IM 8
282 #define CP0St_KX 7
283 #define CP0St_SX 6
284 #define CP0St_UX 5
285 #define CP0St_KSU 3
286 #define CP0St_ERL 2
287 #define CP0St_EXL 1
288 #define CP0St_IE 0
289 int32_t CP0_IntCtl;
290 #define CP0IntCtl_IPTI 29
291 #define CP0IntCtl_IPPC1 26
292 #define CP0IntCtl_VS 5
293 int32_t CP0_SRSCtl;
294 #define CP0SRSCtl_HSS 26
295 #define CP0SRSCtl_EICSS 18
296 #define CP0SRSCtl_ESS 12
297 #define CP0SRSCtl_PSS 6
298 #define CP0SRSCtl_CSS 0
299 int32_t CP0_SRSMap;
300 #define CP0SRSMap_SSV7 28
301 #define CP0SRSMap_SSV6 24
302 #define CP0SRSMap_SSV5 20
303 #define CP0SRSMap_SSV4 16
304 #define CP0SRSMap_SSV3 12
305 #define CP0SRSMap_SSV2 8
306 #define CP0SRSMap_SSV1 4
307 #define CP0SRSMap_SSV0 0
308 int32_t CP0_Cause;
309 #define CP0Ca_BD 31
310 #define CP0Ca_TI 30
311 #define CP0Ca_CE 28
312 #define CP0Ca_DC 27
313 #define CP0Ca_PCI 26
314 #define CP0Ca_IV 23
315 #define CP0Ca_WP 22
316 #define CP0Ca_IP 8
317 #define CP0Ca_IP_mask 0x0000FF00
318 #define CP0Ca_EC 2
319 target_ulong CP0_EPC;
320 int32_t CP0_PRid;
321 int32_t CP0_EBase;
322 int32_t CP0_Config0;
323 #define CP0C0_M 31
324 #define CP0C0_K23 28
325 #define CP0C0_KU 25
326 #define CP0C0_MDU 20
327 #define CP0C0_MM 17
328 #define CP0C0_BM 16
329 #define CP0C0_BE 15
330 #define CP0C0_AT 13
331 #define CP0C0_AR 10
332 #define CP0C0_MT 7
333 #define CP0C0_VI 3
334 #define CP0C0_K0 0
335 int32_t CP0_Config1;
336 #define CP0C1_M 31
337 #define CP0C1_MMU 25
338 #define CP0C1_IS 22
339 #define CP0C1_IL 19
340 #define CP0C1_IA 16
341 #define CP0C1_DS 13
342 #define CP0C1_DL 10
343 #define CP0C1_DA 7
344 #define CP0C1_C2 6
345 #define CP0C1_MD 5
346 #define CP0C1_PC 4
347 #define CP0C1_WR 3
348 #define CP0C1_CA 2
349 #define CP0C1_EP 1
350 #define CP0C1_FP 0
351 int32_t CP0_Config2;
352 #define CP0C2_M 31
353 #define CP0C2_TU 28
354 #define CP0C2_TS 24
355 #define CP0C2_TL 20
356 #define CP0C2_TA 16
357 #define CP0C2_SU 12
358 #define CP0C2_SS 8
359 #define CP0C2_SL 4
360 #define CP0C2_SA 0
361 int32_t CP0_Config3;
362 #define CP0C3_M 31
363 #define CP0C3_DSPP 10
364 #define CP0C3_LPA 7
365 #define CP0C3_VEIC 6
366 #define CP0C3_VInt 5
367 #define CP0C3_SP 4
368 #define CP0C3_MT 2
369 #define CP0C3_SM 1
370 #define CP0C3_TL 0
371 int32_t CP0_Config6;
372 int32_t CP0_Config7;
373 /* XXX: Maybe make LLAddr per-TC? */
374 target_ulong lladdr;
375 target_ulong llval;
376 target_ulong llnewval;
377 target_ulong llreg;
378 target_ulong CP0_LLAddr_rw_bitmask;
379 int CP0_LLAddr_shift;
380 target_ulong CP0_WatchLo[8];
381 int32_t CP0_WatchHi[8];
382 target_ulong CP0_XContext;
383 int32_t CP0_Framemask;
384 int32_t CP0_Debug;
385 #define CP0DB_DBD 31
386 #define CP0DB_DM 30
387 #define CP0DB_LSNM 28
388 #define CP0DB_Doze 27
389 #define CP0DB_Halt 26
390 #define CP0DB_CNT 25
391 #define CP0DB_IBEP 24
392 #define CP0DB_DBEP 21
393 #define CP0DB_IEXI 20
394 #define CP0DB_VER 15
395 #define CP0DB_DEC 10
396 #define CP0DB_SSt 8
397 #define CP0DB_DINT 5
398 #define CP0DB_DIB 4
399 #define CP0DB_DDBS 3
400 #define CP0DB_DDBL 2
401 #define CP0DB_DBp 1
402 #define CP0DB_DSS 0
403 target_ulong CP0_DEPC;
404 int32_t CP0_Performance0;
405 int32_t CP0_TagLo;
406 int32_t CP0_DataLo;
407 int32_t CP0_TagHi;
408 int32_t CP0_DataHi;
409 target_ulong CP0_ErrorEPC;
410 int32_t CP0_DESAVE;
411 /* We waste some space so we can handle shadow registers like TCs. */
412 TCState tcs[MIPS_SHADOW_SET_MAX];
413 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
414 /* Qemu */
415 int error_code;
416 uint32_t hflags; /* CPU State */
417 /* TMASK defines different execution modes */
418 #define MIPS_HFLAG_TMASK 0x03FF
419 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
420 /* The KSU flags must be the lowest bits in hflags. The flag order
421 must be the same as defined for CP0 Status. This allows to use
422 the bits as the value of mmu_idx. */
423 #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
424 #define MIPS_HFLAG_UM 0x0002 /* user mode flag */
425 #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
426 #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
427 #define MIPS_HFLAG_DM 0x0004 /* Debug mode */
428 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
429 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
430 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
431 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
432 /* True if the MIPS IV COP1X instructions can be used. This also
433 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
434 and RSQRT.D. */
435 #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
436 #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
437 #define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */
438 /* If translation is interrupted between the branch instruction and
439 * the delay slot, record what type of branch it is so that we can
440 * resume translation properly. It might be possible to reduce
441 * this from three bits to two. */
442 #define MIPS_HFLAG_BMASK 0x1C00
443 #define MIPS_HFLAG_B 0x0400 /* Unconditional branch */
444 #define MIPS_HFLAG_BC 0x0800 /* Conditional branch */
445 #define MIPS_HFLAG_BL 0x0C00 /* Likely branch */
446 #define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */
447 target_ulong btarget; /* Jump / branch target */
448 target_ulong bcond; /* Branch condition (if needed) */
449
450 int SYNCI_Step; /* Address step size for SYNCI */
451 int CCRes; /* Cycle count resolution/divisor */
452 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
453 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
454 int insn_flags; /* Supported instruction set */
455
456 target_ulong tls_value; /* For usermode emulation */
457
458 CPU_COMMON
459
460 CPUMIPSMVPContext *mvp;
461 CPUMIPSTLBContext *tlb;
462
463 const mips_def_t *cpu_model;
464 void *irq[8];
465 struct QEMUTimer *timer; /* Internal timer */
466 };
467
468 int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
469 target_ulong address, int rw, int access_type);
470 int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
471 target_ulong address, int rw, int access_type);
472 int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
473 target_ulong address, int rw, int access_type);
474 void r4k_helper_tlbwi (void);
475 void r4k_helper_tlbwr (void);
476 void r4k_helper_tlbp (void);
477 void r4k_helper_tlbr (void);
478 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
479
480 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
481 int unused, int size);
482
483 #define cpu_init cpu_mips_init
484 #define cpu_exec cpu_mips_exec
485 #define cpu_gen_code cpu_mips_gen_code
486 #define cpu_signal_handler cpu_mips_signal_handler
487 #define cpu_list mips_cpu_list
488
489 #define CPU_SAVE_VERSION 3
490
491 /* MMU modes definitions. We carefully match the indices with our
492 hflags layout. */
493 #define MMU_MODE0_SUFFIX _kernel
494 #define MMU_MODE1_SUFFIX _super
495 #define MMU_MODE2_SUFFIX _user
496 #define MMU_USER_IDX 2
cpu_mmu_index(CPUState * env)497 static inline int cpu_mmu_index (CPUState *env)
498 {
499 return env->hflags & MIPS_HFLAG_KSU;
500 }
501
is_cpu_user(CPUState * env)502 static inline int is_cpu_user (CPUState *env)
503 {
504 #ifdef CONFIG_USER_ONLY
505 return 1;
506 #else
507 return ((env->CP0_Status &
508 ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU));
509 #endif // CONFIG_USER_ONLY
510 }
511
cpu_clone_regs(CPUState * env,target_ulong newsp)512 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
513 {
514 if (newsp)
515 env->active_tc.gpr[29] = newsp;
516 env->active_tc.gpr[7] = 0;
517 env->active_tc.gpr[2] = 0;
518 }
519
cpu_mips_hw_interrupts_pending(CPUState * env)520 static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
521 {
522 int32_t pending;
523 int32_t status;
524 int r;
525
526 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
527 (env->CP0_Status & (1 << CP0St_EXL)) ||
528 (env->CP0_Status & (1 << CP0St_ERL)) ||
529 (env->hflags & MIPS_HFLAG_DM)) {
530 /* Interrupts are disabled */
531 return 0;
532 }
533
534 pending = env->CP0_Cause & CP0Ca_IP_mask;
535 status = env->CP0_Status & CP0Ca_IP_mask;
536
537 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
538 /* A MIPS configured with a vectorizing external interrupt controller
539 will feed a vector into the Cause pending lines. The core treats
540 the status lines as a vector level, not as indiviual masks. */
541 r = pending > status;
542 } else {
543 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
544 treats the pending lines as individual interrupt lines, the status
545 lines are individual masks. */
546 r = pending & status;
547 }
548 return r;
549 }
550
551 #include "cpu-all.h"
552 #include "exec-all.h"
553
554 /* Memory access type :
555 * may be needed for precise access rights control and precise exceptions.
556 */
557 enum {
558 /* 1 bit to define user level / supervisor access */
559 ACCESS_USER = 0x00,
560 ACCESS_SUPER = 0x01,
561 /* 1 bit to indicate direction */
562 ACCESS_STORE = 0x02,
563 /* Type of instruction that generated the access */
564 ACCESS_CODE = 0x10, /* Code fetch access */
565 ACCESS_INT = 0x20, /* Integer load/store access */
566 ACCESS_FLOAT = 0x30, /* floating point load/store access */
567 };
568
569 /* Exceptions */
570 enum {
571 EXCP_NONE = -1,
572 EXCP_RESET = 0,
573 EXCP_SRESET,
574 EXCP_DSS,
575 EXCP_DINT,
576 EXCP_DDBL,
577 EXCP_DDBS,
578 EXCP_NMI,
579 EXCP_MCHECK,
580 EXCP_EXT_INTERRUPT, /* 8 */
581 EXCP_DFWATCH,
582 EXCP_DIB,
583 EXCP_IWATCH,
584 EXCP_AdEL,
585 EXCP_AdES,
586 EXCP_TLBF,
587 EXCP_IBE,
588 EXCP_DBp, /* 16 */
589 EXCP_SYSCALL,
590 EXCP_BREAK,
591 EXCP_CpU,
592 EXCP_RI,
593 EXCP_OVERFLOW,
594 EXCP_TRAP,
595 EXCP_FPE,
596 EXCP_DWATCH, /* 24 */
597 EXCP_LTLBL,
598 EXCP_TLBL,
599 EXCP_TLBS,
600 EXCP_DBE,
601 EXCP_THREAD,
602 EXCP_MDMX,
603 EXCP_C2E,
604 EXCP_CACHE, /* 32 */
605
606 EXCP_LAST = EXCP_CACHE,
607 };
608 /* Dummy exception for conditional stores. */
609 #define EXCP_SC 0x100
610
611 int cpu_mips_exec(CPUMIPSState *s);
612 CPUMIPSState *cpu_mips_init(const char *cpu_model);
613 //~ uint32_t cpu_mips_get_clock (void);
614 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
615
616 /* mips_timer.c */
617 uint32_t cpu_mips_get_random (CPUState *env);
618 uint32_t cpu_mips_get_count (CPUState *env);
619 void cpu_mips_store_count (CPUState *env, uint32_t value);
620 void cpu_mips_store_compare (CPUState *env, uint32_t value);
621 void cpu_mips_start_count(CPUState *env);
622 void cpu_mips_stop_count(CPUState *env);
623
624 /* mips_int.c */
625 void cpu_mips_update_irq (CPUState *env);
626
627 /* helper.c */
628 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
629 int mmu_idx, int is_softmmu);
630 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
631 void do_interrupt (CPUState *env);
632 target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
633 int rw);
634
cpu_pc_from_tb(CPUState * env,TranslationBlock * tb)635 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
636 {
637 env->active_tc.PC = tb->pc;
638 env->hflags &= ~MIPS_HFLAG_BMASK;
639 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
640 }
641
cpu_get_tb_cpu_state(CPUState * env,target_ulong * pc,target_ulong * cs_base,int * flags)642 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
643 target_ulong *cs_base, int *flags)
644 {
645 *pc = env->active_tc.PC;
646 *cs_base = 0;
647 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
648 }
649
cpu_set_tls(CPUState * env,target_ulong newtls)650 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
651 {
652 env->tls_value = newtls;
653 }
654
655 #endif /* !defined (__MIPS_CPU_H__) */
656