1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11 // instructions after register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "postrapseudos"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27
28 namespace {
29 struct ExpandPostRA : public MachineFunctionPass {
30 private:
31 const TargetRegisterInfo *TRI;
32 const TargetInstrInfo *TII;
33
34 public:
35 static char ID; // Pass identification, replacement for typeid
ExpandPostRA__anonbbddaff80111::ExpandPostRA36 ExpandPostRA() : MachineFunctionPass(ID) {}
37
getAnalysisUsage__anonbbddaff80111::ExpandPostRA38 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
39 AU.setPreservesCFG();
40 AU.addPreservedID(MachineLoopInfoID);
41 AU.addPreservedID(MachineDominatorsID);
42 MachineFunctionPass::getAnalysisUsage(AU);
43 }
44
45 /// runOnMachineFunction - pass entry point
46 bool runOnMachineFunction(MachineFunction&);
47
48 private:
49 bool LowerSubregToReg(MachineInstr *MI);
50 bool LowerCopy(MachineInstr *MI);
51
52 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
53 const TargetRegisterInfo *TRI);
54 void TransferImplicitDefs(MachineInstr *MI);
55 };
56 } // end anonymous namespace
57
58 char ExpandPostRA::ID = 0;
59 char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
60
61 INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
62 "Post-RA pseudo instruction expansion pass", false, false)
63
64 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
65 /// and the lowered replacement instructions immediately precede it.
66 /// Mark the replacement instructions with the dead flag.
67 void
TransferDeadFlag(MachineInstr * MI,unsigned DstReg,const TargetRegisterInfo * TRI)68 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
69 const TargetRegisterInfo *TRI) {
70 for (MachineBasicBlock::iterator MII =
71 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
72 if (MII->addRegisterDead(DstReg, TRI))
73 break;
74 assert(MII != MI->getParent()->begin() &&
75 "copyPhysReg output doesn't reference destination register!");
76 }
77 }
78
79 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
80 /// replacement instructions immediately precede it. Copy any implicit-def
81 /// operands from MI to the replacement instruction.
82 void
TransferImplicitDefs(MachineInstr * MI)83 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
84 MachineBasicBlock::iterator CopyMI = MI;
85 --CopyMI;
86
87 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
88 MachineOperand &MO = MI->getOperand(i);
89 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
90 continue;
91 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
92 }
93 }
94
LowerSubregToReg(MachineInstr * MI)95 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
96 MachineBasicBlock *MBB = MI->getParent();
97 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
98 MI->getOperand(1).isImm() &&
99 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
100 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
101
102 unsigned DstReg = MI->getOperand(0).getReg();
103 unsigned InsReg = MI->getOperand(2).getReg();
104 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
105 unsigned SubIdx = MI->getOperand(3).getImm();
106
107 assert(SubIdx != 0 && "Invalid index for insert_subreg");
108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
109
110 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
111 "Insert destination must be in a physical register");
112 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
113 "Inserted value must be in a physical register");
114
115 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
116
117 if (DstSubReg == InsReg) {
118 // No need to insert an identify copy instruction.
119 // Watch out for case like this:
120 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
121 // We must leave %RAX live.
122 if (DstReg != InsReg) {
123 MI->setDesc(TII->get(TargetOpcode::KILL));
124 MI->RemoveOperand(3); // SubIdx
125 MI->RemoveOperand(1); // Imm
126 DEBUG(dbgs() << "subreg: replace by: " << *MI);
127 return true;
128 }
129 DEBUG(dbgs() << "subreg: eliminated!");
130 } else {
131 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
132 MI->getOperand(2).isKill());
133
134 // Implicitly define DstReg for subsequent uses.
135 MachineBasicBlock::iterator CopyMI = MI;
136 --CopyMI;
137 CopyMI->addRegisterDefined(DstReg);
138
139 // Transfer the kill/dead flags, if needed.
140 if (MI->getOperand(0).isDead())
141 TransferDeadFlag(MI, DstSubReg, TRI);
142 DEBUG(dbgs() << "subreg: " << *CopyMI);
143 }
144
145 DEBUG(dbgs() << '\n');
146 MBB->erase(MI);
147 return true;
148 }
149
LowerCopy(MachineInstr * MI)150 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
151 MachineOperand &DstMO = MI->getOperand(0);
152 MachineOperand &SrcMO = MI->getOperand(1);
153
154 if (SrcMO.getReg() == DstMO.getReg()) {
155 DEBUG(dbgs() << "identity copy: " << *MI);
156 // No need to insert an identity copy instruction, but replace with a KILL
157 // if liveness is changed.
158 if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
159 // We must make sure the super-register gets killed. Replace the
160 // instruction with KILL.
161 MI->setDesc(TII->get(TargetOpcode::KILL));
162 DEBUG(dbgs() << "replaced by: " << *MI);
163 return true;
164 }
165 // Vanilla identity copy.
166 MI->eraseFromParent();
167 return true;
168 }
169
170 DEBUG(dbgs() << "real copy: " << *MI);
171 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
172 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
173
174 if (DstMO.isDead())
175 TransferDeadFlag(MI, DstMO.getReg(), TRI);
176 if (MI->getNumOperands() > 2)
177 TransferImplicitDefs(MI);
178 DEBUG({
179 MachineBasicBlock::iterator dMI = MI;
180 dbgs() << "replaced by: " << *(--dMI);
181 });
182 MI->eraseFromParent();
183 return true;
184 }
185
186 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
187 /// copies.
188 ///
runOnMachineFunction(MachineFunction & MF)189 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
190 DEBUG(dbgs() << "Machine Function\n"
191 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
192 << "********** Function: " << MF.getName() << '\n');
193 TRI = MF.getTarget().getRegisterInfo();
194 TII = MF.getTarget().getInstrInfo();
195
196 bool MadeChange = false;
197
198 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
199 mbbi != mbbe; ++mbbi) {
200 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
201 mi != me;) {
202 MachineInstr *MI = mi;
203 // Advance iterator here because MI may be erased.
204 ++mi;
205
206 // Only expand pseudos.
207 if (!MI->isPseudo())
208 continue;
209
210 // Give targets a chance to expand even standard pseudos.
211 if (TII->expandPostRAPseudo(MI)) {
212 MadeChange = true;
213 continue;
214 }
215
216 // Expand standard pseudos.
217 switch (MI->getOpcode()) {
218 case TargetOpcode::SUBREG_TO_REG:
219 MadeChange |= LowerSubregToReg(MI);
220 break;
221 case TargetOpcode::COPY:
222 MadeChange |= LowerCopy(MI);
223 break;
224 case TargetOpcode::DBG_VALUE:
225 continue;
226 case TargetOpcode::INSERT_SUBREG:
227 case TargetOpcode::EXTRACT_SUBREG:
228 llvm_unreachable("Sub-register pseudos should have been eliminated.");
229 }
230 }
231 }
232
233 return MadeChange;
234 }
235