1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "AsmWriterInst.h"
17 #include "CodeGenTarget.h"
18 #include "llvm/MC/EDInstInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/Format.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/TableGen/Record.h"
23 #include "llvm/TableGen/TableGenBackend.h"
24 #include <string>
25 #include <vector>
26
27 using namespace llvm;
28
29 // TODO: There's a suspiciously large amount of "table" data in this
30 // backend which should probably be in the TableGen file itself.
31
32 ///////////////////////////////////////////////////////////
33 // Support classes for emitting nested C data structures //
34 ///////////////////////////////////////////////////////////
35
36 // TODO: These classes are probably generally useful to other backends;
37 // add them to TableGen's "helper" API's.
38
39 namespace {
40 class EnumEmitter {
41 private:
42 std::string Name;
43 std::vector<std::string> Entries;
44 public:
EnumEmitter(const char * N)45 EnumEmitter(const char *N) : Name(N) {
46 }
addEntry(const char * e)47 int addEntry(const char *e) {
48 Entries.push_back(std::string(e));
49 return Entries.size() - 1;
50 }
emit(raw_ostream & o,unsigned int & i)51 void emit(raw_ostream &o, unsigned int &i) {
52 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
53 i += 2;
54
55 unsigned int index = 0;
56 unsigned int numEntries = Entries.size();
57 for (index = 0; index < numEntries; ++index) {
58 o.indent(i) << Entries[index];
59 if (index < (numEntries - 1))
60 o << ",";
61 o << "\n";
62 }
63
64 i -= 2;
65 o.indent(i) << "};" << "\n";
66 }
67
emitAsFlags(raw_ostream & o,unsigned int & i)68 void emitAsFlags(raw_ostream &o, unsigned int &i) {
69 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
70 i += 2;
71
72 unsigned int index = 0;
73 unsigned int numEntries = Entries.size();
74 unsigned int flag = 1;
75 for (index = 0; index < numEntries; ++index) {
76 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
77 if (index < (numEntries - 1))
78 o << ",";
79 o << "\n";
80 flag <<= 1;
81 }
82
83 i -= 2;
84 o.indent(i) << "};" << "\n";
85 }
86 };
87 } // End anonymous namespace
88
89 namespace {
90 class ConstantEmitter {
91 public:
~ConstantEmitter()92 virtual ~ConstantEmitter() { }
93 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
94 };
95 } // End anonymous namespace
96
97 namespace {
98 class LiteralConstantEmitter : public ConstantEmitter {
99 private:
100 bool IsNumber;
101 union {
102 int Number;
103 const char* String;
104 };
105 public:
LiteralConstantEmitter(int number=0)106 LiteralConstantEmitter(int number = 0) :
107 IsNumber(true),
108 Number(number) {
109 }
set(const char * string)110 void set(const char *string) {
111 IsNumber = false;
112 Number = 0;
113 String = string;
114 }
is(const char * string)115 bool is(const char *string) {
116 return !strcmp(String, string);
117 }
emit(raw_ostream & o,unsigned int & i)118 void emit(raw_ostream &o, unsigned int &i) {
119 if (IsNumber)
120 o << Number;
121 else
122 o << String;
123 }
124 };
125 } // End anonymous namespace
126
127 namespace {
128 class CompoundConstantEmitter : public ConstantEmitter {
129 private:
130 unsigned int Padding;
131 std::vector<ConstantEmitter *> Entries;
132 public:
CompoundConstantEmitter(unsigned int padding=0)133 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
134 }
addEntry(ConstantEmitter * e)135 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
136 Entries.push_back(e);
137
138 return *this;
139 }
~CompoundConstantEmitter()140 ~CompoundConstantEmitter() {
141 while (Entries.size()) {
142 ConstantEmitter *entry = Entries.back();
143 Entries.pop_back();
144 delete entry;
145 }
146 }
emit(raw_ostream & o,unsigned int & i)147 void emit(raw_ostream &o, unsigned int &i) {
148 o << "{" << "\n";
149 i += 2;
150
151 unsigned int index;
152 unsigned int numEntries = Entries.size();
153
154 unsigned int numToPrint;
155
156 if (Padding) {
157 if (numEntries > Padding) {
158 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
159 llvm_unreachable("More entries than padding");
160 }
161 numToPrint = Padding;
162 } else {
163 numToPrint = numEntries;
164 }
165
166 for (index = 0; index < numToPrint; ++index) {
167 o.indent(i);
168 if (index < numEntries)
169 Entries[index]->emit(o, i);
170 else
171 o << "-1";
172
173 if (index < (numToPrint - 1))
174 o << ",";
175 o << "\n";
176 }
177
178 i -= 2;
179 o.indent(i) << "}";
180 }
181 };
182 } // End anonymous namespace
183
184 namespace {
185 class FlagsConstantEmitter : public ConstantEmitter {
186 private:
187 std::vector<std::string> Flags;
188 public:
FlagsConstantEmitter()189 FlagsConstantEmitter() {
190 }
addEntry(const char * f)191 FlagsConstantEmitter &addEntry(const char *f) {
192 Flags.push_back(std::string(f));
193 return *this;
194 }
emit(raw_ostream & o,unsigned int & i)195 void emit(raw_ostream &o, unsigned int &i) {
196 unsigned int index;
197 unsigned int numFlags = Flags.size();
198 if (numFlags == 0)
199 o << "0";
200
201 for (index = 0; index < numFlags; ++index) {
202 o << Flags[index].c_str();
203 if (index < (numFlags - 1))
204 o << " | ";
205 }
206 }
207 };
208 } // End anonymous namespace
209
210 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
211 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
212 /// operands in the order they appear in the printed instruction. Then, for
213 /// each entry in that list, determines the index of the same operand in the
214 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
215 /// in unused slots with -1.
216 ///
217 /// @arg operandOrder - The array that will be populated with the operand
218 /// mapping. Each entry will contain -1 (invalid index
219 /// into the operands present in the AsmString) or a number
220 /// representing an index in the operand descriptor array.
221 /// @arg inst - The instruction to use when looking up the operands
222 /// @arg syntax - The syntax to use, according to LLVM's enumeration
populateOperandOrder(CompoundConstantEmitter * operandOrder,const CodeGenInstruction & inst,unsigned syntax)223 static void populateOperandOrder(CompoundConstantEmitter *operandOrder,
224 const CodeGenInstruction &inst,
225 unsigned syntax) {
226 unsigned int numArgs = 0;
227
228 AsmWriterInst awInst(inst, syntax, -1, -1);
229
230 std::vector<AsmWriterOperand>::iterator operandIterator;
231
232 for (operandIterator = awInst.Operands.begin();
233 operandIterator != awInst.Operands.end();
234 ++operandIterator) {
235 if (operandIterator->OperandType ==
236 AsmWriterOperand::isMachineInstrOperand) {
237 operandOrder->addEntry(
238 new LiteralConstantEmitter(operandIterator->CGIOpNo));
239 numArgs++;
240 }
241 }
242 }
243
244 /////////////////////////////////////////////////////
245 // Support functions for handling X86 instructions //
246 /////////////////////////////////////////////////////
247
248 #define SET(flag) { type->set(flag); return 0; }
249
250 #define REG(str) if (name == str) SET("kOperandTypeRegister");
251 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
252 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
253 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
254 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
255
256 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
257 /// actually its type) and translates it into an operand type
258 ///
259 /// @arg flags - The type object to set
260 /// @arg name - The name of the operand
X86TypeFromOpName(LiteralConstantEmitter * type,const std::string & name)261 static int X86TypeFromOpName(LiteralConstantEmitter *type,
262 const std::string &name) {
263 REG("GR8");
264 REG("GR8_NOREX");
265 REG("GR16");
266 REG("GR16_NOAX");
267 REG("GR32");
268 REG("GR32_NOAX");
269 REG("GR32_NOREX");
270 REG("GR32_TC");
271 REG("FR32");
272 REG("RFP32");
273 REG("GR64");
274 REG("GR64_NOAX");
275 REG("GR64_TC");
276 REG("FR64");
277 REG("VR64");
278 REG("RFP64");
279 REG("RFP80");
280 REG("VR128");
281 REG("VR256");
282 REG("RST");
283 REG("SEGMENT_REG");
284 REG("DEBUG_REG");
285 REG("CONTROL_REG");
286
287 IMM("i8imm");
288 IMM("i16imm");
289 IMM("i16i8imm");
290 IMM("i32imm");
291 IMM("i32i8imm");
292 IMM("u32u8imm");
293 IMM("i64imm");
294 IMM("i64i8imm");
295 IMM("i64i32imm");
296 IMM("SSECC");
297 IMM("AVXCC");
298
299 // all R, I, R, I, R
300 MEM("i8mem");
301 MEM("i8mem_NOREX");
302 MEM("i16mem");
303 MEM("i32mem");
304 MEM("i32mem_TC");
305 MEM("f32mem");
306 MEM("ssmem");
307 MEM("opaque32mem");
308 MEM("opaque48mem");
309 MEM("i64mem");
310 MEM("i64mem_TC");
311 MEM("f64mem");
312 MEM("sdmem");
313 MEM("f80mem");
314 MEM("opaque80mem");
315 MEM("i128mem");
316 MEM("i256mem");
317 MEM("f128mem");
318 MEM("f256mem");
319 MEM("opaque512mem");
320 // Gather
321 MEM("vx32mem")
322 MEM("vy32mem")
323 MEM("vx64mem")
324 MEM("vy64mem")
325
326 // all R, I, R, I
327 LEA("lea32mem");
328 LEA("lea64_32mem");
329 LEA("lea64mem");
330
331 // all I
332 PCR("i16imm_pcrel");
333 PCR("i32imm_pcrel");
334 PCR("i64i32imm_pcrel");
335 PCR("brtarget8");
336 PCR("offset8");
337 PCR("offset16");
338 PCR("offset32");
339 PCR("offset64");
340 PCR("brtarget");
341 PCR("uncondbrtarget");
342 PCR("bltarget");
343
344 // all I, ARM mode only, conditional/unconditional
345 PCR("br_target");
346 PCR("bl_target");
347 return 1;
348 }
349
350 #undef REG
351 #undef MEM
352 #undef LEA
353 #undef IMM
354 #undef PCR
355
356 #undef SET
357
358 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
359 /// the appropriate flags to their descriptors
360 ///
361 /// @operandFlags - A reference the array of operand flag objects
362 /// @inst - The instruction to use as a source of information
X86PopulateOperands(LiteralConstantEmitter * (& operandTypes)[EDIS_MAX_OPERANDS],const CodeGenInstruction & inst)363 static void X86PopulateOperands(
364 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
365 const CodeGenInstruction &inst) {
366 if (!inst.TheDef->isSubClassOf("X86Inst"))
367 return;
368
369 unsigned int index;
370 unsigned int numOperands = inst.Operands.size();
371
372 for (index = 0; index < numOperands; ++index) {
373 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
374 Record &rec = *operandInfo.Rec;
375
376 if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
377 !rec.isSubClassOf("PointerLikeRegClass")) {
378 errs() << "Operand type: " << rec.getName().c_str() << "\n";
379 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
380 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
381 llvm_unreachable("Unhandled type");
382 }
383 }
384 }
385
386 /// decorate1 - Decorates a named operand with a new flag
387 ///
388 /// @operandFlags - The array of operand flag objects, which don't have names
389 /// @inst - The CodeGenInstruction, which provides a way to translate
390 /// between names and operand indices
391 /// @opName - The name of the operand
392 /// @flag - The name of the flag to add
decorate1(FlagsConstantEmitter * (& operandFlags)[EDIS_MAX_OPERANDS],const CodeGenInstruction & inst,const char * opName,const char * opFlag)393 static inline void decorate1(
394 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
395 const CodeGenInstruction &inst,
396 const char *opName,
397 const char *opFlag) {
398 unsigned opIndex;
399
400 opIndex = inst.Operands.getOperandNamed(std::string(opName));
401
402 operandFlags[opIndex]->addEntry(opFlag);
403 }
404
405 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
406
407 #define MOV(source, target) { \
408 instType.set("kInstructionTypeMove"); \
409 DECORATE1(source, "kOperandFlagSource"); \
410 DECORATE1(target, "kOperandFlagTarget"); \
411 }
412
413 #define BRANCH(target) { \
414 instType.set("kInstructionTypeBranch"); \
415 DECORATE1(target, "kOperandFlagTarget"); \
416 }
417
418 #define PUSH(source) { \
419 instType.set("kInstructionTypePush"); \
420 DECORATE1(source, "kOperandFlagSource"); \
421 }
422
423 #define POP(target) { \
424 instType.set("kInstructionTypePop"); \
425 DECORATE1(target, "kOperandFlagTarget"); \
426 }
427
428 #define CALL(target) { \
429 instType.set("kInstructionTypeCall"); \
430 DECORATE1(target, "kOperandFlagTarget"); \
431 }
432
433 #define RETURN() { \
434 instType.set("kInstructionTypeReturn"); \
435 }
436
437 /// X86ExtractSemantics - Performs various checks on the name of an X86
438 /// instruction to determine what sort of an instruction it is and then adds
439 /// the appropriate flags to the instruction and its operands
440 ///
441 /// @arg instType - A reference to the type for the instruction as a whole
442 /// @arg operandFlags - A reference to the array of operand flag object pointers
443 /// @arg inst - A reference to the original instruction
X86ExtractSemantics(LiteralConstantEmitter & instType,FlagsConstantEmitter * (& operandFlags)[EDIS_MAX_OPERANDS],const CodeGenInstruction & inst)444 static void X86ExtractSemantics(
445 LiteralConstantEmitter &instType,
446 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
447 const CodeGenInstruction &inst) {
448 const std::string &name = inst.TheDef->getName();
449
450 if (name.find("MOV") != name.npos) {
451 if (name.find("MOV_V") != name.npos) {
452 // ignore (this is a pseudoinstruction)
453 } else if (name.find("MASK") != name.npos) {
454 // ignore (this is a masking move)
455 } else if (name.find("r0") != name.npos) {
456 // ignore (this is a pseudoinstruction)
457 } else if (name.find("PS") != name.npos ||
458 name.find("PD") != name.npos) {
459 // ignore (this is a shuffling move)
460 } else if (name.find("MOVS") != name.npos) {
461 // ignore (this is a string move)
462 } else if (name.find("_F") != name.npos) {
463 // TODO handle _F moves to ST(0)
464 } else if (name.find("a") != name.npos) {
465 // TODO handle moves to/from %ax
466 } else if (name.find("CMOV") != name.npos) {
467 MOV("src2", "dst");
468 } else if (name.find("PC") != name.npos) {
469 MOV("label", "reg")
470 } else {
471 MOV("src", "dst");
472 }
473 }
474
475 if (name.find("JMP") != name.npos ||
476 name.find("J") == 0) {
477 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
478 BRANCH("off");
479 } else {
480 BRANCH("dst");
481 }
482 }
483
484 if (name.find("PUSH") != name.npos) {
485 if (name.find("CS") != name.npos ||
486 name.find("DS") != name.npos ||
487 name.find("ES") != name.npos ||
488 name.find("FS") != name.npos ||
489 name.find("GS") != name.npos ||
490 name.find("SS") != name.npos) {
491 instType.set("kInstructionTypePush");
492 // TODO add support for fixed operands
493 } else if (name.find("F") != name.npos) {
494 // ignore (this pushes onto the FP stack)
495 } else if (name.find("A") != name.npos) {
496 // ignore (pushes all GP registoers onto the stack)
497 } else if (name[name.length() - 1] == 'm') {
498 PUSH("src");
499 } else if (name.find("i") != name.npos) {
500 PUSH("imm");
501 } else {
502 PUSH("reg");
503 }
504 }
505
506 if (name.find("POP") != name.npos) {
507 if (name.find("POPCNT") != name.npos) {
508 // ignore (not a real pop)
509 } else if (name.find("CS") != name.npos ||
510 name.find("DS") != name.npos ||
511 name.find("ES") != name.npos ||
512 name.find("FS") != name.npos ||
513 name.find("GS") != name.npos ||
514 name.find("SS") != name.npos) {
515 instType.set("kInstructionTypePop");
516 // TODO add support for fixed operands
517 } else if (name.find("F") != name.npos) {
518 // ignore (this pops from the FP stack)
519 } else if (name.find("A") != name.npos) {
520 // ignore (pushes all GP registoers onto the stack)
521 } else if (name[name.length() - 1] == 'm') {
522 POP("dst");
523 } else {
524 POP("reg");
525 }
526 }
527
528 if (name.find("CALL") != name.npos) {
529 if (name.find("ADJ") != name.npos) {
530 // ignore (not a call)
531 } else if (name.find("SYSCALL") != name.npos) {
532 // ignore (doesn't go anywhere we know about)
533 } else if (name.find("VMCALL") != name.npos) {
534 // ignore (rather different semantics than a regular call)
535 } else if (name.find("VMMCALL") != name.npos) {
536 // ignore (rather different semantics than a regular call)
537 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
538 CALL("off");
539 } else {
540 CALL("dst");
541 }
542 }
543
544 if (name.find("RET") != name.npos) {
545 RETURN();
546 }
547 }
548
549 #undef MOV
550 #undef BRANCH
551 #undef PUSH
552 #undef POP
553 #undef CALL
554 #undef RETURN
555
556 /////////////////////////////////////////////////////
557 // Support functions for handling ARM instructions //
558 /////////////////////////////////////////////////////
559
560 #define SET(flag) { type->set(flag); return 0; }
561
562 #define REG(str) if (name == str) SET("kOperandTypeRegister");
563 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
564
565 #define MISC(str, type) if (name == str) SET(type);
566
567 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
568 /// actually its type) and translates it into an operand type
569 ///
570 /// @arg type - The type object to set
571 /// @arg name - The name of the operand
ARMFlagFromOpName(LiteralConstantEmitter * type,const std::string & name)572 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
573 const std::string &name) {
574 REG("GPR");
575 REG("rGPR");
576 REG("GPRnopc");
577 REG("GPRsp");
578 REG("tcGPR");
579 REG("cc_out");
580 REG("s_cc_out");
581 REG("tGPR");
582 REG("DPR");
583 REG("DPR_VFP2");
584 REG("DPR_8");
585 REG("DPair");
586 REG("SPR");
587 REG("QPR");
588 REG("QQPR");
589 REG("QQQQPR");
590 REG("VecListOneD");
591 REG("VecListDPair");
592 REG("VecListDPairSpaced");
593 REG("VecListThreeD");
594 REG("VecListFourD");
595 REG("VecListOneDAllLanes");
596 REG("VecListDPairAllLanes");
597 REG("VecListDPairSpacedAllLanes");
598
599 IMM("i32imm");
600 IMM("fbits16");
601 IMM("fbits32");
602 IMM("i32imm_hilo16");
603 IMM("bf_inv_mask_imm");
604 IMM("lsb_pos_imm");
605 IMM("width_imm");
606 IMM("jtblock_operand");
607 IMM("nohash_imm");
608 IMM("p_imm");
609 IMM("pf_imm");
610 IMM("c_imm");
611 IMM("coproc_option_imm");
612 IMM("imod_op");
613 IMM("iflags_op");
614 IMM("cpinst_operand");
615 IMM("setend_op");
616 IMM("cps_opt");
617 IMM("vfp_f64imm");
618 IMM("vfp_f32imm");
619 IMM("memb_opt");
620 IMM("msr_mask");
621 IMM("neg_zero");
622 IMM("imm0_31");
623 IMM("imm0_31_m1");
624 IMM("imm1_16");
625 IMM("imm1_32");
626 IMM("nModImm");
627 IMM("nImmSplatI8");
628 IMM("nImmSplatI16");
629 IMM("nImmSplatI32");
630 IMM("nImmSplatI64");
631 IMM("nImmVMOVI32");
632 IMM("nImmVMOVF32");
633 IMM("imm8");
634 IMM("imm16");
635 IMM("imm32");
636 IMM("imm1_7");
637 IMM("imm1_15");
638 IMM("imm1_31");
639 IMM("imm0_1");
640 IMM("imm0_3");
641 IMM("imm0_7");
642 IMM("imm0_15");
643 IMM("imm0_255");
644 IMM("imm0_4095");
645 IMM("imm0_65535");
646 IMM("imm0_65535_expr");
647 IMM("imm24b");
648 IMM("pkh_lsl_amt");
649 IMM("pkh_asr_amt");
650 IMM("jt2block_operand");
651 IMM("t_imm0_1020s4");
652 IMM("t_imm0_508s4");
653 IMM("pclabel");
654 IMM("adrlabel");
655 IMM("t_adrlabel");
656 IMM("t2adrlabel");
657 IMM("shift_imm");
658 IMM("t2_shift_imm");
659 IMM("neon_vcvt_imm32");
660 IMM("shr_imm8");
661 IMM("shr_imm16");
662 IMM("shr_imm32");
663 IMM("shr_imm64");
664 IMM("t2ldrlabel");
665 IMM("postidx_imm8");
666 IMM("postidx_imm8s4");
667 IMM("imm_sr");
668 IMM("imm1_31");
669 IMM("VectorIndex8");
670 IMM("VectorIndex16");
671 IMM("VectorIndex32");
672
673 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
674 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
675 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
676 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
677 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
678 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
679
680 MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
681 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
682 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ?
683
684 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
685 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
686 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
687 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
688 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
689 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
690 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
691 MISC("so_imm", "kOperandTypeARMSoImm"); // I
692 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
693 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
694 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
695 MISC("pred", "kOperandTypeARMPredicate"); // I, R
696 MISC("it_pred", "kOperandTypeARMPredicate"); // I
697 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
698 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
699 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I
700 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
701 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
702 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
703 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
704 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
705 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
706 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
707 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
708 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
709 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
710 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
711 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
712 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
713 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
714 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
715 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
716 MISC("it_mask", "kOperandTypeThumbITMask"); // I
717 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R
718 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
719 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
720 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
721 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
722 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
723 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
724 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
725 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
726 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
727 // R, I
728 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
729 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R
730 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R
731 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R
732 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I
733 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I
734 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I
735 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
736 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
737 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
738 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R
739 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R
740
741 return 1;
742 }
743
744 #undef REG
745 #undef MEM
746 #undef MISC
747
748 #undef SET
749
750 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
751 /// the appropriate flags to their descriptors
752 ///
753 /// @operandFlags - A reference the array of operand flag objects
754 /// @inst - The instruction to use as a source of information
ARMPopulateOperands(LiteralConstantEmitter * (& operandTypes)[EDIS_MAX_OPERANDS],const CodeGenInstruction & inst)755 static void ARMPopulateOperands(
756 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
757 const CodeGenInstruction &inst) {
758 if (!inst.TheDef->isSubClassOf("InstARM") &&
759 !inst.TheDef->isSubClassOf("InstThumb"))
760 return;
761
762 unsigned int index;
763 unsigned int numOperands = inst.Operands.size();
764
765 if (numOperands > EDIS_MAX_OPERANDS) {
766 errs() << "numOperands == " << numOperands << " > " <<
767 EDIS_MAX_OPERANDS << '\n';
768 llvm_unreachable("Too many operands");
769 }
770
771 for (index = 0; index < numOperands; ++index) {
772 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
773 Record &rec = *operandInfo.Rec;
774
775 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
776 errs() << "Operand type: " << rec.getName() << '\n';
777 errs() << "Operand name: " << operandInfo.Name << '\n';
778 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
779 throw("Unhandled type in EDEmitter");
780 }
781 }
782 }
783
784 #define BRANCH(target) { \
785 instType.set("kInstructionTypeBranch"); \
786 DECORATE1(target, "kOperandFlagTarget"); \
787 }
788
789 /// ARMExtractSemantics - Performs various checks on the name of an ARM
790 /// instruction to determine what sort of an instruction it is and then adds
791 /// the appropriate flags to the instruction and its operands
792 ///
793 /// @arg instType - A reference to the type for the instruction as a whole
794 /// @arg operandTypes - A reference to the array of operand type object pointers
795 /// @arg operandFlags - A reference to the array of operand flag object pointers
796 /// @arg inst - A reference to the original instruction
ARMExtractSemantics(LiteralConstantEmitter & instType,LiteralConstantEmitter * (& operandTypes)[EDIS_MAX_OPERANDS],FlagsConstantEmitter * (& operandFlags)[EDIS_MAX_OPERANDS],const CodeGenInstruction & inst)797 static void ARMExtractSemantics(
798 LiteralConstantEmitter &instType,
799 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
800 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
801 const CodeGenInstruction &inst) {
802 const std::string &name = inst.TheDef->getName();
803
804 if (name == "tBcc" ||
805 name == "tB" ||
806 name == "t2Bcc" ||
807 name == "Bcc" ||
808 name == "tCBZ" ||
809 name == "tCBNZ") {
810 BRANCH("target");
811 }
812
813 if (name == "tBLr9" ||
814 name == "BLr9_pred" ||
815 name == "tBLXi_r9" ||
816 name == "tBLXr_r9" ||
817 name == "BLXr9" ||
818 name == "t2BXJ" ||
819 name == "BXJ") {
820 BRANCH("func");
821
822 unsigned opIndex;
823 opIndex = inst.Operands.getOperandNamed("func");
824 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
825 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
826 }
827 }
828
829 #undef BRANCH
830
831 /// populateInstInfo - Fills an array of InstInfos with information about each
832 /// instruction in a target
833 ///
834 /// @arg infoArray - The array of InstInfo objects to populate
835 /// @arg target - The CodeGenTarget to use as a source of instructions
populateInstInfo(CompoundConstantEmitter & infoArray,CodeGenTarget & target)836 static void populateInstInfo(CompoundConstantEmitter &infoArray,
837 CodeGenTarget &target) {
838 const std::vector<const CodeGenInstruction*> &numberedInstructions =
839 target.getInstructionsByEnumValue();
840
841 unsigned int index;
842 unsigned int numInstructions = numberedInstructions.size();
843
844 for (index = 0; index < numInstructions; ++index) {
845 const CodeGenInstruction& inst = *numberedInstructions[index];
846
847 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
848 infoArray.addEntry(infoStruct);
849
850 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
851 infoStruct->addEntry(instType);
852
853 LiteralConstantEmitter *numOperandsEmitter =
854 new LiteralConstantEmitter(inst.Operands.size());
855 infoStruct->addEntry(numOperandsEmitter);
856
857 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
858 infoStruct->addEntry(operandTypeArray);
859
860 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
861
862 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
863 infoStruct->addEntry(operandFlagArray);
864
865 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
866
867 for (unsigned operandIndex = 0;
868 operandIndex < EDIS_MAX_OPERANDS;
869 ++operandIndex) {
870 operandTypes[operandIndex] = new LiteralConstantEmitter;
871 operandTypeArray->addEntry(operandTypes[operandIndex]);
872
873 operandFlags[operandIndex] = new FlagsConstantEmitter;
874 operandFlagArray->addEntry(operandFlags[operandIndex]);
875 }
876
877 unsigned numSyntaxes = 0;
878
879 // We don't need to do anything for pseudo-instructions, as we'll never
880 // see them here. We'll only see real instructions.
881 // We still need to emit null initializers for everything.
882 if (!inst.isPseudo) {
883 if (target.getName() == "X86") {
884 X86PopulateOperands(operandTypes, inst);
885 X86ExtractSemantics(*instType, operandFlags, inst);
886 numSyntaxes = 2;
887 }
888 else if (target.getName() == "ARM") {
889 ARMPopulateOperands(operandTypes, inst);
890 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
891 numSyntaxes = 1;
892 }
893 }
894
895 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
896
897 infoStruct->addEntry(operandOrderArray);
898
899 for (unsigned syntaxIndex = 0;
900 syntaxIndex < EDIS_MAX_SYNTAXES;
901 ++syntaxIndex) {
902 CompoundConstantEmitter *operandOrder =
903 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
904
905 operandOrderArray->addEntry(operandOrder);
906
907 if (syntaxIndex < numSyntaxes) {
908 populateOperandOrder(operandOrder, inst, syntaxIndex);
909 }
910 }
911
912 infoStruct = NULL;
913 }
914 }
915
emitCommonEnums(raw_ostream & o,unsigned int & i)916 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
917 EnumEmitter operandTypes("OperandTypes");
918 operandTypes.addEntry("kOperandTypeNone");
919 operandTypes.addEntry("kOperandTypeImmediate");
920 operandTypes.addEntry("kOperandTypeRegister");
921 operandTypes.addEntry("kOperandTypeX86Memory");
922 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
923 operandTypes.addEntry("kOperandTypeX86PCRelative");
924 operandTypes.addEntry("kOperandTypeARMBranchTarget");
925 operandTypes.addEntry("kOperandTypeARMSoRegReg");
926 operandTypes.addEntry("kOperandTypeARMSoRegImm");
927 operandTypes.addEntry("kOperandTypeARMSoImm");
928 operandTypes.addEntry("kOperandTypeARMRotImm");
929 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
930 operandTypes.addEntry("kOperandTypeARMPredicate");
931 operandTypes.addEntry("kOperandTypeAddrModeImm12");
932 operandTypes.addEntry("kOperandTypeLdStSOReg");
933 operandTypes.addEntry("kOperandTypeARMAddrMode2");
934 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
935 operandTypes.addEntry("kOperandTypeARMAddrMode3");
936 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
937 operandTypes.addEntry("kOperandTypeARMLdStmMode");
938 operandTypes.addEntry("kOperandTypeARMAddrMode5");
939 operandTypes.addEntry("kOperandTypeARMAddrMode6");
940 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
941 operandTypes.addEntry("kOperandTypeARMAddrMode7");
942 operandTypes.addEntry("kOperandTypeARMAddrModePC");
943 operandTypes.addEntry("kOperandTypeARMRegisterList");
944 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
945 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
946 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
947 operandTypes.addEntry("kOperandTypeThumbITMask");
948 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
949 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
950 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
951 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
952 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
953 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
954 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
955 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
956 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
957 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
958 operandTypes.addEntry("kOperandTypeThumb2SoReg");
959 operandTypes.addEntry("kOperandTypeThumb2SoImm");
960 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
961 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
962 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
963 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
964 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
965 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
966 operandTypes.emit(o, i);
967
968 o << "\n";
969
970 EnumEmitter operandFlags("OperandFlags");
971 operandFlags.addEntry("kOperandFlagSource");
972 operandFlags.addEntry("kOperandFlagTarget");
973 operandFlags.emitAsFlags(o, i);
974
975 o << "\n";
976
977 EnumEmitter instructionTypes("InstructionTypes");
978 instructionTypes.addEntry("kInstructionTypeNone");
979 instructionTypes.addEntry("kInstructionTypeMove");
980 instructionTypes.addEntry("kInstructionTypeBranch");
981 instructionTypes.addEntry("kInstructionTypePush");
982 instructionTypes.addEntry("kInstructionTypePop");
983 instructionTypes.addEntry("kInstructionTypeCall");
984 instructionTypes.addEntry("kInstructionTypeReturn");
985 instructionTypes.emit(o, i);
986
987 o << "\n";
988 }
989
990 namespace llvm {
991
EmitEnhancedDisassemblerInfo(RecordKeeper & RK,raw_ostream & OS)992 void EmitEnhancedDisassemblerInfo(RecordKeeper &RK, raw_ostream &OS) {
993 emitSourceFileHeader("Enhanced Disassembler Info", OS);
994 unsigned int i = 0;
995
996 CompoundConstantEmitter infoArray;
997 CodeGenTarget target(RK);
998
999 populateInstInfo(infoArray, target);
1000
1001 emitCommonEnums(OS, i);
1002
1003 OS << "static const llvm::EDInstInfo instInfo"
1004 << target.getName() << "[] = ";
1005 infoArray.emit(OS, i);
1006 OS << ";" << "\n";
1007 }
1008
1009 } // End llvm namespace
1010