• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineOperand class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
15 #define LLVM_CODEGEN_MACHINEOPERAND_H
16 
17 #include "llvm/Support/DataTypes.h"
18 #include <cassert>
19 
20 namespace llvm {
21 
22 class BlockAddress;
23 class ConstantFP;
24 class ConstantInt;
25 class GlobalValue;
26 class MachineBasicBlock;
27 class MachineInstr;
28 class MachineRegisterInfo;
29 class MDNode;
30 class TargetMachine;
31 class TargetRegisterInfo;
32 class hash_code;
33 class raw_ostream;
34 class MCSymbol;
35 
36 /// MachineOperand class - Representation of each machine instruction operand.
37 ///
38 class MachineOperand {
39 public:
40   enum MachineOperandType {
41     MO_Register,               ///< Register operand.
42     MO_Immediate,              ///< Immediate operand
43     MO_CImmediate,             ///< Immediate >64bit operand
44     MO_FPImmediate,            ///< Floating-point immediate operand
45     MO_MachineBasicBlock,      ///< MachineBasicBlock reference
46     MO_FrameIndex,             ///< Abstract Stack Frame Index
47     MO_ConstantPoolIndex,      ///< Address of indexed Constant in Constant Pool
48     MO_TargetIndex,            ///< Target-dependent index+offset operand.
49     MO_JumpTableIndex,         ///< Address of indexed Jump Table for switch
50     MO_ExternalSymbol,         ///< Name of external global symbol
51     MO_GlobalAddress,          ///< Address of a global value
52     MO_BlockAddress,           ///< Address of a basic block
53     MO_RegisterMask,           ///< Mask of preserved registers.
54     MO_Metadata,               ///< Metadata reference (for debug info)
55     MO_MCSymbol                ///< MCSymbol reference (for debug/eh info)
56   };
57 
58 private:
59   /// OpKind - Specify what kind of operand this is.  This discriminates the
60   /// union.
61   unsigned char OpKind; // MachineOperandType
62 
63   // This union is discriminated by OpKind.
64   union {
65     /// SubReg - Subregister number, only valid for MO_Register.  A value of 0
66     /// indicates the MO_Register has no subReg.
67     unsigned char SubReg;
68 
69     /// TargetFlags - This is a set of target-specific operand flags.
70     unsigned char TargetFlags;
71   };
72 
73   /// TiedTo - Non-zero when this register operand is tied to another register
74   /// operand. The encoding of this field is described in the block comment
75   /// before MachineInstr::tieOperands().
76   unsigned char TiedTo : 4;
77 
78   /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
79   /// operands.
80 
81   /// IsDef - True if this is a def, false if this is a use of the register.
82   ///
83   bool IsDef : 1;
84 
85   /// IsImp - True if this is an implicit def or use, false if it is explicit.
86   ///
87   bool IsImp : 1;
88 
89   /// IsKill - True if this instruction is the last use of the register on this
90   /// path through the function.  This is only valid on uses of registers.
91   bool IsKill : 1;
92 
93   /// IsDead - True if this register is never used by a subsequent instruction.
94   /// This is only valid on definitions of registers.
95   bool IsDead : 1;
96 
97   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
98   /// read value doesn't matter.  This flag can be set on both use and def
99   /// operands.  On a sub-register def operand, it refers to the part of the
100   /// register that isn't written.  On a full-register def operand, it is a
101   /// noop.  See readsReg().
102   ///
103   /// This is only valid on registers.
104   ///
105   /// Note that an instruction may have multiple <undef> operands referring to
106   /// the same register.  In that case, the instruction may depend on those
107   /// operands reading the same dont-care value.  For example:
108   ///
109   ///   %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
110   ///
111   /// Any register can be used for %vreg2, and its value doesn't matter, but
112   /// the two operands must be the same register.
113   ///
114   bool IsUndef : 1;
115 
116   /// IsInternalRead - True if this operand reads a value that was defined
117   /// inside the same instruction or bundle.  This flag can be set on both use
118   /// and def operands.  On a sub-register def operand, it refers to the part
119   /// of the register that isn't written.  On a full-register def operand, it
120   /// is a noop.
121   ///
122   /// When this flag is set, the instruction bundle must contain at least one
123   /// other def of the register.  If multiple instructions in the bundle define
124   /// the register, the meaning is target-defined.
125   bool IsInternalRead : 1;
126 
127   /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
128   /// by the MachineInstr before all input registers are read.  This is used to
129   /// model the GCC inline asm '&' constraint modifier.
130   bool IsEarlyClobber : 1;
131 
132   /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
133   /// not a real instruction.  Such uses should be ignored during codegen.
134   bool IsDebug : 1;
135 
136   /// SmallContents - This really should be part of the Contents union, but
137   /// lives out here so we can get a better packed struct.
138   /// MO_Register: Register number.
139   /// OffsetedInfo: Low bits of offset.
140   union {
141     unsigned RegNo;           // For MO_Register.
142     unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
143   } SmallContents;
144 
145   /// ParentMI - This is the instruction that this operand is embedded into.
146   /// This is valid for all operand types, when the operand is in an instr.
147   MachineInstr *ParentMI;
148 
149   /// Contents union - This contains the payload for the various operand types.
150   union {
151     MachineBasicBlock *MBB;   // For MO_MachineBasicBlock.
152     const ConstantFP *CFP;    // For MO_FPImmediate.
153     const ConstantInt *CI;    // For MO_CImmediate. Integers > 64bit.
154     int64_t ImmVal;           // For MO_Immediate.
155     const uint32_t *RegMask;  // For MO_RegisterMask.
156     const MDNode *MD;         // For MO_Metadata.
157     MCSymbol *Sym;            // For MO_MCSymbol
158 
159     struct {                  // For MO_Register.
160       // Register number is in SmallContents.RegNo.
161       MachineOperand *Prev;   // Access list for register. See MRI.
162       MachineOperand *Next;
163     } Reg;
164 
165     /// OffsetedInfo - This struct contains the offset and an object identifier.
166     /// this represent the object as with an optional offset from it.
167     struct {
168       union {
169         int Index;                // For MO_*Index - The index itself.
170         const char *SymbolName;   // For MO_ExternalSymbol.
171         const GlobalValue *GV;    // For MO_GlobalAddress.
172         const BlockAddress *BA;   // For MO_BlockAddress.
173       } Val;
174       // Low bits of offset are in SmallContents.OffsetLo.
175       int OffsetHi;               // An offset from the object, high 32 bits.
176     } OffsetedInfo;
177   } Contents;
178 
MachineOperand(MachineOperandType K)179   explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
180     TargetFlags = 0;
181   }
182 public:
183   /// getType - Returns the MachineOperandType for this operand.
184   ///
getType()185   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
186 
getTargetFlags()187   unsigned char getTargetFlags() const {
188     return isReg() ? 0 : TargetFlags;
189   }
setTargetFlags(unsigned char F)190   void setTargetFlags(unsigned char F) {
191     assert(!isReg() && "Register operands can't have target flags");
192     TargetFlags = F;
193   }
addTargetFlag(unsigned char F)194   void addTargetFlag(unsigned char F) {
195     assert(!isReg() && "Register operands can't have target flags");
196     TargetFlags |= F;
197   }
198 
199 
200   /// getParent - Return the instruction that this operand belongs to.
201   ///
getParent()202   MachineInstr *getParent() { return ParentMI; }
getParent()203   const MachineInstr *getParent() const { return ParentMI; }
204 
205   /// clearParent - Reset the parent pointer.
206   ///
207   /// The MachineOperand copy constructor also copies ParentMI, expecting the
208   /// original to be deleted. If a MachineOperand is ever stored outside a
209   /// MachineInstr, the parent pointer must be cleared.
210   ///
211   /// Never call clearParent() on an operand in a MachineInstr.
212   ///
clearParent()213   void clearParent() { ParentMI = 0; }
214 
215   void print(raw_ostream &os, const TargetMachine *TM = 0) const;
216 
217   //===--------------------------------------------------------------------===//
218   // Accessors that tell you what kind of MachineOperand you're looking at.
219   //===--------------------------------------------------------------------===//
220 
221   /// isReg - Tests if this is a MO_Register operand.
isReg()222   bool isReg() const { return OpKind == MO_Register; }
223   /// isImm - Tests if this is a MO_Immediate operand.
isImm()224   bool isImm() const { return OpKind == MO_Immediate; }
225   /// isCImm - Test if t his is a MO_CImmediate operand.
isCImm()226   bool isCImm() const { return OpKind == MO_CImmediate; }
227   /// isFPImm - Tests if this is a MO_FPImmediate operand.
isFPImm()228   bool isFPImm() const { return OpKind == MO_FPImmediate; }
229   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
isMBB()230   bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
231   /// isFI - Tests if this is a MO_FrameIndex operand.
isFI()232   bool isFI() const { return OpKind == MO_FrameIndex; }
233   /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
isCPI()234   bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
235   /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
isTargetIndex()236   bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
237   /// isJTI - Tests if this is a MO_JumpTableIndex operand.
isJTI()238   bool isJTI() const { return OpKind == MO_JumpTableIndex; }
239   /// isGlobal - Tests if this is a MO_GlobalAddress operand.
isGlobal()240   bool isGlobal() const { return OpKind == MO_GlobalAddress; }
241   /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
isSymbol()242   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
243   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
isBlockAddress()244   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
245   /// isRegMask - Tests if this is a MO_RegisterMask operand.
isRegMask()246   bool isRegMask() const { return OpKind == MO_RegisterMask; }
247   /// isMetadata - Tests if this is a MO_Metadata operand.
isMetadata()248   bool isMetadata() const { return OpKind == MO_Metadata; }
isMCSymbol()249   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
250 
251 
252   //===--------------------------------------------------------------------===//
253   // Accessors for Register Operands
254   //===--------------------------------------------------------------------===//
255 
256   /// getReg - Returns the register number.
getReg()257   unsigned getReg() const {
258     assert(isReg() && "This is not a register operand!");
259     return SmallContents.RegNo;
260   }
261 
getSubReg()262   unsigned getSubReg() const {
263     assert(isReg() && "Wrong MachineOperand accessor");
264     return (unsigned)SubReg;
265   }
266 
isUse()267   bool isUse() const {
268     assert(isReg() && "Wrong MachineOperand accessor");
269     return !IsDef;
270   }
271 
isDef()272   bool isDef() const {
273     assert(isReg() && "Wrong MachineOperand accessor");
274     return IsDef;
275   }
276 
isImplicit()277   bool isImplicit() const {
278     assert(isReg() && "Wrong MachineOperand accessor");
279     return IsImp;
280   }
281 
isDead()282   bool isDead() const {
283     assert(isReg() && "Wrong MachineOperand accessor");
284     return IsDead;
285   }
286 
isKill()287   bool isKill() const {
288     assert(isReg() && "Wrong MachineOperand accessor");
289     return IsKill;
290   }
291 
isUndef()292   bool isUndef() const {
293     assert(isReg() && "Wrong MachineOperand accessor");
294     return IsUndef;
295   }
296 
isInternalRead()297   bool isInternalRead() const {
298     assert(isReg() && "Wrong MachineOperand accessor");
299     return IsInternalRead;
300   }
301 
isEarlyClobber()302   bool isEarlyClobber() const {
303     assert(isReg() && "Wrong MachineOperand accessor");
304     return IsEarlyClobber;
305   }
306 
isTied()307   bool isTied() const {
308     assert(isReg() && "Wrong MachineOperand accessor");
309     return TiedTo;
310   }
311 
isDebug()312   bool isDebug() const {
313     assert(isReg() && "Wrong MachineOperand accessor");
314     return IsDebug;
315   }
316 
317   /// readsReg - Returns true if this operand reads the previous value of its
318   /// register.  A use operand with the <undef> flag set doesn't read its
319   /// register.  A sub-register def implicitly reads the other parts of the
320   /// register being redefined unless the <undef> flag is set.
321   ///
322   /// This refers to reading the register value from before the current
323   /// instruction or bundle. Internal bundle reads are not included.
readsReg()324   bool readsReg() const {
325     assert(isReg() && "Wrong MachineOperand accessor");
326     return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
327   }
328 
329   //===--------------------------------------------------------------------===//
330   // Mutators for Register Operands
331   //===--------------------------------------------------------------------===//
332 
333   /// Change the register this operand corresponds to.
334   ///
335   void setReg(unsigned Reg);
336 
setSubReg(unsigned subReg)337   void setSubReg(unsigned subReg) {
338     assert(isReg() && "Wrong MachineOperand accessor");
339     SubReg = (unsigned char)subReg;
340   }
341 
342   /// substVirtReg - Substitute the current register with the virtual
343   /// subregister Reg:SubReg. Take any existing SubReg index into account,
344   /// using TargetRegisterInfo to compose the subreg indices if necessary.
345   /// Reg must be a virtual register, SubIdx can be 0.
346   ///
347   void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
348 
349   /// substPhysReg - Substitute the current register with the physical register
350   /// Reg, taking any existing SubReg into account. For instance,
351   /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
352   ///
353   void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
354 
355   void setIsUse(bool Val = true) { setIsDef(!Val); }
356 
357   void setIsDef(bool Val = true);
358 
359   void setImplicit(bool Val = true) {
360     assert(isReg() && "Wrong MachineOperand accessor");
361     IsImp = Val;
362   }
363 
364   void setIsKill(bool Val = true) {
365     assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
366     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
367     IsKill = Val;
368   }
369 
370   void setIsDead(bool Val = true) {
371     assert(isReg() && IsDef && "Wrong MachineOperand accessor");
372     IsDead = Val;
373   }
374 
375   void setIsUndef(bool Val = true) {
376     assert(isReg() && "Wrong MachineOperand accessor");
377     IsUndef = Val;
378   }
379 
380   void setIsInternalRead(bool Val = true) {
381     assert(isReg() && "Wrong MachineOperand accessor");
382     IsInternalRead = Val;
383   }
384 
385   void setIsEarlyClobber(bool Val = true) {
386     assert(isReg() && IsDef && "Wrong MachineOperand accessor");
387     IsEarlyClobber = Val;
388   }
389 
390   void setIsDebug(bool Val = true) {
391     assert(isReg() && IsDef && "Wrong MachineOperand accessor");
392     IsDebug = Val;
393   }
394 
395   //===--------------------------------------------------------------------===//
396   // Accessors for various operand types.
397   //===--------------------------------------------------------------------===//
398 
getImm()399   int64_t getImm() const {
400     assert(isImm() && "Wrong MachineOperand accessor");
401     return Contents.ImmVal;
402   }
403 
getCImm()404   const ConstantInt *getCImm() const {
405     assert(isCImm() && "Wrong MachineOperand accessor");
406     return Contents.CI;
407   }
408 
getFPImm()409   const ConstantFP *getFPImm() const {
410     assert(isFPImm() && "Wrong MachineOperand accessor");
411     return Contents.CFP;
412   }
413 
getMBB()414   MachineBasicBlock *getMBB() const {
415     assert(isMBB() && "Wrong MachineOperand accessor");
416     return Contents.MBB;
417   }
418 
getIndex()419   int getIndex() const {
420     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
421            "Wrong MachineOperand accessor");
422     return Contents.OffsetedInfo.Val.Index;
423   }
424 
getGlobal()425   const GlobalValue *getGlobal() const {
426     assert(isGlobal() && "Wrong MachineOperand accessor");
427     return Contents.OffsetedInfo.Val.GV;
428   }
429 
getBlockAddress()430   const BlockAddress *getBlockAddress() const {
431     assert(isBlockAddress() && "Wrong MachineOperand accessor");
432     return Contents.OffsetedInfo.Val.BA;
433   }
434 
getMCSymbol()435   MCSymbol *getMCSymbol() const {
436     assert(isMCSymbol() && "Wrong MachineOperand accessor");
437     return Contents.Sym;
438   }
439 
440   /// getOffset - Return the offset from the symbol in this operand. This always
441   /// returns 0 for ExternalSymbol operands.
getOffset()442   int64_t getOffset() const {
443     assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
444             isBlockAddress()) && "Wrong MachineOperand accessor");
445     return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
446            SmallContents.OffsetLo;
447   }
448 
getSymbolName()449   const char *getSymbolName() const {
450     assert(isSymbol() && "Wrong MachineOperand accessor");
451     return Contents.OffsetedInfo.Val.SymbolName;
452   }
453 
454   /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
455   /// It is sometimes necessary to detach the register mask pointer from its
456   /// machine operand. This static method can be used for such detached bit
457   /// mask pointers.
clobbersPhysReg(const uint32_t * RegMask,unsigned PhysReg)458   static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
459     // See TargetRegisterInfo.h.
460     assert(PhysReg < (1u << 30) && "Not a physical register");
461     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
462   }
463 
464   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
clobbersPhysReg(unsigned PhysReg)465   bool clobbersPhysReg(unsigned PhysReg) const {
466      return clobbersPhysReg(getRegMask(), PhysReg);
467   }
468 
469   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
470   /// operand.
getRegMask()471   const uint32_t *getRegMask() const {
472     assert(isRegMask() && "Wrong MachineOperand accessor");
473     return Contents.RegMask;
474   }
475 
getMetadata()476   const MDNode *getMetadata() const {
477     assert(isMetadata() && "Wrong MachineOperand accessor");
478     return Contents.MD;
479   }
480 
481   //===--------------------------------------------------------------------===//
482   // Mutators for various operand types.
483   //===--------------------------------------------------------------------===//
484 
setImm(int64_t immVal)485   void setImm(int64_t immVal) {
486     assert(isImm() && "Wrong MachineOperand mutator");
487     Contents.ImmVal = immVal;
488   }
489 
setOffset(int64_t Offset)490   void setOffset(int64_t Offset) {
491     assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
492             isBlockAddress()) && "Wrong MachineOperand accessor");
493     SmallContents.OffsetLo = unsigned(Offset);
494     Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
495   }
496 
setIndex(int Idx)497   void setIndex(int Idx) {
498     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
499            "Wrong MachineOperand accessor");
500     Contents.OffsetedInfo.Val.Index = Idx;
501   }
502 
setMBB(MachineBasicBlock * MBB)503   void setMBB(MachineBasicBlock *MBB) {
504     assert(isMBB() && "Wrong MachineOperand accessor");
505     Contents.MBB = MBB;
506   }
507 
508   //===--------------------------------------------------------------------===//
509   // Other methods.
510   //===--------------------------------------------------------------------===//
511 
512   /// isIdenticalTo - Return true if this operand is identical to the specified
513   /// operand. Note: This method ignores isKill and isDead properties.
514   bool isIdenticalTo(const MachineOperand &Other) const;
515 
516   /// \brief MachineOperand hash_value overload.
517   ///
518   /// Note that this includes the same information in the hash that
519   /// isIdenticalTo uses for comparison. It is thus suited for use in hash
520   /// tables which use that function for equality comparisons only.
521   friend hash_code hash_value(const MachineOperand &MO);
522 
523   /// ChangeToImmediate - Replace this operand with a new immediate operand of
524   /// the specified value.  If an operand is known to be an immediate already,
525   /// the setImm method should be used.
526   void ChangeToImmediate(int64_t ImmVal);
527 
528   /// ChangeToRegister - Replace this operand with a new register operand of
529   /// the specified value.  If an operand is known to be an register already,
530   /// the setReg method should be used.
531   void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
532                         bool isKill = false, bool isDead = false,
533                         bool isUndef = false, bool isDebug = false);
534 
535   //===--------------------------------------------------------------------===//
536   // Construction methods.
537   //===--------------------------------------------------------------------===//
538 
CreateImm(int64_t Val)539   static MachineOperand CreateImm(int64_t Val) {
540     MachineOperand Op(MachineOperand::MO_Immediate);
541     Op.setImm(Val);
542     return Op;
543   }
544 
CreateCImm(const ConstantInt * CI)545   static MachineOperand CreateCImm(const ConstantInt *CI) {
546     MachineOperand Op(MachineOperand::MO_CImmediate);
547     Op.Contents.CI = CI;
548     return Op;
549   }
550 
CreateFPImm(const ConstantFP * CFP)551   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
552     MachineOperand Op(MachineOperand::MO_FPImmediate);
553     Op.Contents.CFP = CFP;
554     return Op;
555   }
556 
557   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
558                                   bool isKill = false, bool isDead = false,
559                                   bool isUndef = false,
560                                   bool isEarlyClobber = false,
561                                   unsigned SubReg = 0,
562                                   bool isDebug = false,
563                                   bool isInternalRead = false) {
564     MachineOperand Op(MachineOperand::MO_Register);
565     Op.IsDef = isDef;
566     Op.IsImp = isImp;
567     Op.IsKill = isKill;
568     Op.IsDead = isDead;
569     Op.IsUndef = isUndef;
570     Op.IsInternalRead = isInternalRead;
571     Op.IsEarlyClobber = isEarlyClobber;
572     Op.TiedTo = 0;
573     Op.IsDebug = isDebug;
574     Op.SmallContents.RegNo = Reg;
575     Op.Contents.Reg.Prev = 0;
576     Op.Contents.Reg.Next = 0;
577     Op.SubReg = SubReg;
578     return Op;
579   }
580   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
581                                   unsigned char TargetFlags = 0) {
582     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
583     Op.setMBB(MBB);
584     Op.setTargetFlags(TargetFlags);
585     return Op;
586   }
CreateFI(int Idx)587   static MachineOperand CreateFI(int Idx) {
588     MachineOperand Op(MachineOperand::MO_FrameIndex);
589     Op.setIndex(Idx);
590     return Op;
591   }
592   static MachineOperand CreateCPI(unsigned Idx, int Offset,
593                                   unsigned char TargetFlags = 0) {
594     MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
595     Op.setIndex(Idx);
596     Op.setOffset(Offset);
597     Op.setTargetFlags(TargetFlags);
598     return Op;
599   }
600   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
601                                           unsigned char TargetFlags = 0) {
602     MachineOperand Op(MachineOperand::MO_TargetIndex);
603     Op.setIndex(Idx);
604     Op.setOffset(Offset);
605     Op.setTargetFlags(TargetFlags);
606     return Op;
607   }
608   static MachineOperand CreateJTI(unsigned Idx,
609                                   unsigned char TargetFlags = 0) {
610     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
611     Op.setIndex(Idx);
612     Op.setTargetFlags(TargetFlags);
613     return Op;
614   }
615   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
616                                  unsigned char TargetFlags = 0) {
617     MachineOperand Op(MachineOperand::MO_GlobalAddress);
618     Op.Contents.OffsetedInfo.Val.GV = GV;
619     Op.setOffset(Offset);
620     Op.setTargetFlags(TargetFlags);
621     return Op;
622   }
623   static MachineOperand CreateES(const char *SymName,
624                                  unsigned char TargetFlags = 0) {
625     MachineOperand Op(MachineOperand::MO_ExternalSymbol);
626     Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
627     Op.setOffset(0); // Offset is always 0.
628     Op.setTargetFlags(TargetFlags);
629     return Op;
630   }
631   static MachineOperand CreateBA(const BlockAddress *BA,
632                                  unsigned char TargetFlags = 0) {
633     MachineOperand Op(MachineOperand::MO_BlockAddress);
634     Op.Contents.OffsetedInfo.Val.BA = BA;
635     Op.setOffset(0); // Offset is always 0.
636     Op.setTargetFlags(TargetFlags);
637     return Op;
638   }
639   /// CreateRegMask - Creates a register mask operand referencing Mask.  The
640   /// operand does not take ownership of the memory referenced by Mask, it must
641   /// remain valid for the lifetime of the operand.
642   ///
643   /// A RegMask operand represents a set of non-clobbered physical registers on
644   /// an instruction that clobbers many registers, typically a call.  The bit
645   /// mask has a bit set for each physreg that is preserved by this
646   /// instruction, as described in the documentation for
647   /// TargetRegisterInfo::getCallPreservedMask().
648   ///
649   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
650   ///
CreateRegMask(const uint32_t * Mask)651   static MachineOperand CreateRegMask(const uint32_t *Mask) {
652     assert(Mask && "Missing register mask");
653     MachineOperand Op(MachineOperand::MO_RegisterMask);
654     Op.Contents.RegMask = Mask;
655     return Op;
656   }
CreateMetadata(const MDNode * Meta)657   static MachineOperand CreateMetadata(const MDNode *Meta) {
658     MachineOperand Op(MachineOperand::MO_Metadata);
659     Op.Contents.MD = Meta;
660     return Op;
661   }
662 
CreateMCSymbol(MCSymbol * Sym)663   static MachineOperand CreateMCSymbol(MCSymbol *Sym) {
664     MachineOperand Op(MachineOperand::MO_MCSymbol);
665     Op.Contents.Sym = Sym;
666     return Op;
667   }
668 
669   friend class MachineInstr;
670   friend class MachineRegisterInfo;
671 private:
672   //===--------------------------------------------------------------------===//
673   // Methods for handling register use/def lists.
674   //===--------------------------------------------------------------------===//
675 
676   /// isOnRegUseList - Return true if this operand is on a register use/def list
677   /// or false if not.  This can only be called for register operands that are
678   /// part of a machine instruction.
isOnRegUseList()679   bool isOnRegUseList() const {
680     assert(isReg() && "Can only add reg operand to use lists");
681     return Contents.Reg.Prev != 0;
682   }
683 };
684 
685 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
686   MO.print(OS, 0);
687   return OS;
688 }
689 
690 } // End llvm namespace
691 
692 #endif
693