1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides a MachineSchedRegistry for registering alternative machine 11 // schedulers. A Target may provide an alternative scheduler implementation by 12 // implementing the following boilerplate: 13 // 14 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) { 15 // return new CustomMachineScheduler(C); 16 // } 17 // static MachineSchedRegistry 18 // SchedCustomRegistry("custom", "Run my target's custom scheduler", 19 // createCustomMachineSched); 20 // 21 // Inside <Target>PassConfig: 22 // enablePass(&MachineSchedulerID); 23 // MachineSchedRegistry::setDefault(createCustomMachineSched); 24 // 25 //===----------------------------------------------------------------------===// 26 27 #ifndef MACHINESCHEDULER_H 28 #define MACHINESCHEDULER_H 29 30 #include "llvm/CodeGen/MachinePassRegistry.h" 31 32 namespace llvm { 33 34 class AliasAnalysis; 35 class LiveIntervals; 36 class MachineDominatorTree; 37 class MachineLoopInfo; 38 class RegisterClassInfo; 39 class ScheduleDAGInstrs; 40 41 /// MachineSchedContext provides enough context from the MachineScheduler pass 42 /// for the target to instantiate a scheduler. 43 struct MachineSchedContext { 44 MachineFunction *MF; 45 const MachineLoopInfo *MLI; 46 const MachineDominatorTree *MDT; 47 const TargetPassConfig *PassConfig; 48 AliasAnalysis *AA; 49 LiveIntervals *LIS; 50 51 RegisterClassInfo *RegClassInfo; 52 53 MachineSchedContext(); 54 virtual ~MachineSchedContext(); 55 }; 56 57 /// MachineSchedRegistry provides a selection of available machine instruction 58 /// schedulers. 59 class MachineSchedRegistry : public MachinePassRegistryNode { 60 public: 61 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *); 62 63 // RegisterPassParser requires a (misnamed) FunctionPassCtor type. 64 typedef ScheduleDAGCtor FunctionPassCtor; 65 66 static MachinePassRegistry Registry; 67 MachineSchedRegistry(const char * N,const char * D,ScheduleDAGCtor C)68 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C) 69 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) { 70 Registry.Add(this); 71 } ~MachineSchedRegistry()72 ~MachineSchedRegistry() { Registry.Remove(this); } 73 74 // Accessors. 75 // getNext()76 MachineSchedRegistry *getNext() const { 77 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext(); 78 } getList()79 static MachineSchedRegistry *getList() { 80 return (MachineSchedRegistry *)Registry.getList(); 81 } getDefault()82 static ScheduleDAGCtor getDefault() { 83 return (ScheduleDAGCtor)Registry.getDefault(); 84 } setDefault(ScheduleDAGCtor C)85 static void setDefault(ScheduleDAGCtor C) { 86 Registry.setDefault((MachinePassCtor)C); 87 } setDefault(StringRef Name)88 static void setDefault(StringRef Name) { 89 Registry.setDefault(Name); 90 } setListener(MachinePassRegistryListener * L)91 static void setListener(MachinePassRegistryListener *L) { 92 Registry.setListener(L); 93 } 94 }; 95 96 } // namespace llvm 97 98 #endif 99