1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20
21 #include "llvm/Support/ErrorHandling.h"
22
23 #include <string>
24
25 using namespace llvm;
26
27 #define MRM_MAPPING \
28 MAP(C1, 33) \
29 MAP(C2, 34) \
30 MAP(C3, 35) \
31 MAP(C4, 36) \
32 MAP(C8, 37) \
33 MAP(C9, 38) \
34 MAP(E8, 39) \
35 MAP(F0, 40) \
36 MAP(F8, 41) \
37 MAP(F9, 42) \
38 MAP(D0, 45) \
39 MAP(D1, 46) \
40 MAP(D4, 47) \
41 MAP(D8, 48) \
42 MAP(D9, 49) \
43 MAP(DA, 50) \
44 MAP(DB, 51) \
45 MAP(DC, 52) \
46 MAP(DD, 53) \
47 MAP(DE, 54) \
48 MAP(DF, 55)
49
50 // A clone of X86 since we can't depend on something that is generated.
51 namespace X86Local {
52 enum {
53 Pseudo = 0,
54 RawFrm = 1,
55 AddRegFrm = 2,
56 MRMDestReg = 3,
57 MRMDestMem = 4,
58 MRMSrcReg = 5,
59 MRMSrcMem = 6,
60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
64 MRMInitReg = 32,
65 RawFrmImm8 = 43,
66 RawFrmImm16 = 44,
67 #define MAP(from, to) MRM_##from = to,
68 MRM_MAPPING
69 #undef MAP
70 lastMRM
71 };
72
73 enum {
74 TB = 1,
75 REP = 2,
76 D8 = 3, D9 = 4, DA = 5, DB = 6,
77 DC = 7, DD = 8, DE = 9, DF = 10,
78 XD = 11, XS = 12,
79 T8 = 13, P_TA = 14,
80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
81 };
82 }
83
84 // If rows are added to the opcode extension tables, then corresponding entries
85 // must be added here.
86 //
87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
88 // that byte to ONE_BYTE_EXTENSION_TABLES.
89 //
90 // If the row corresponds to two bytes where the first is 0f, add an entry for
91 // the second byte to TWO_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to some other set of bytes, you will need to modify
94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95 // to the X86 TD files, except in two cases: if the first two bytes of such a
96 // new combination are 0f 38 or 0f 3a, you just have to add maps called
97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99 // in RecognizableInstr::emitDecodePath().
100
101 #define ONE_BYTE_EXTENSION_TABLES \
102 EXTENSION_TABLE(80) \
103 EXTENSION_TABLE(81) \
104 EXTENSION_TABLE(82) \
105 EXTENSION_TABLE(83) \
106 EXTENSION_TABLE(8f) \
107 EXTENSION_TABLE(c0) \
108 EXTENSION_TABLE(c1) \
109 EXTENSION_TABLE(c6) \
110 EXTENSION_TABLE(c7) \
111 EXTENSION_TABLE(d0) \
112 EXTENSION_TABLE(d1) \
113 EXTENSION_TABLE(d2) \
114 EXTENSION_TABLE(d3) \
115 EXTENSION_TABLE(f6) \
116 EXTENSION_TABLE(f7) \
117 EXTENSION_TABLE(fe) \
118 EXTENSION_TABLE(ff)
119
120 #define TWO_BYTE_EXTENSION_TABLES \
121 EXTENSION_TABLE(00) \
122 EXTENSION_TABLE(01) \
123 EXTENSION_TABLE(18) \
124 EXTENSION_TABLE(71) \
125 EXTENSION_TABLE(72) \
126 EXTENSION_TABLE(73) \
127 EXTENSION_TABLE(ae) \
128 EXTENSION_TABLE(ba) \
129 EXTENSION_TABLE(c7)
130
131 #define THREE_BYTE_38_EXTENSION_TABLES \
132 EXTENSION_TABLE(F3)
133
134 using namespace X86Disassembler;
135
136 /// needsModRMForDecode - Indicates whether a particular instruction requires a
137 /// ModR/M byte for the instruction to be properly decoded. For example, a
138 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
139 /// 0b11.
140 ///
141 /// @param form - The form of the instruction.
142 /// @return - true if the form implies that a ModR/M byte is required, false
143 /// otherwise.
needsModRMForDecode(uint8_t form)144 static bool needsModRMForDecode(uint8_t form) {
145 if (form == X86Local::MRMDestReg ||
146 form == X86Local::MRMDestMem ||
147 form == X86Local::MRMSrcReg ||
148 form == X86Local::MRMSrcMem ||
149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
151 return true;
152 else
153 return false;
154 }
155
156 /// isRegFormat - Indicates whether a particular form requires the Mod field of
157 /// the ModR/M byte to be 0b11.
158 ///
159 /// @param form - The form of the instruction.
160 /// @return - true if the form implies that Mod must be 0b11, false
161 /// otherwise.
isRegFormat(uint8_t form)162 static bool isRegFormat(uint8_t form) {
163 if (form == X86Local::MRMDestReg ||
164 form == X86Local::MRMSrcReg ||
165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
166 return true;
167 else
168 return false;
169 }
170
171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172 /// Useful for switch statements and the like.
173 ///
174 /// @param init - A reference to the BitsInit to be decoded.
175 /// @return - The field, with the first bit in the BitsInit as the lowest
176 /// order bit.
byteFromBitsInit(BitsInit & init)177 static uint8_t byteFromBitsInit(BitsInit &init) {
178 int width = init.getNumBits();
179
180 assert(width <= 8 && "Field is too large for uint8_t!");
181
182 int index;
183 uint8_t mask = 0x01;
184
185 uint8_t ret = 0;
186
187 for (index = 0; index < width; index++) {
188 if (static_cast<BitInit*>(init.getBit(index))->getValue())
189 ret |= mask;
190
191 mask <<= 1;
192 }
193
194 return ret;
195 }
196
197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198 /// name of the field.
199 ///
200 /// @param rec - The record from which to extract the value.
201 /// @param name - The name of the field in the record.
202 /// @return - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,const std::string & name)203 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204 BitsInit* bits = rec->getValueAsBitsInit(name);
205 return byteFromBitsInit(*bits);
206 }
207
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209 const CodeGenInstruction &insn,
210 InstrUID uid) {
211 UID = uid;
212
213 Rec = insn.TheDef;
214 Name = Rec->getName();
215 Spec = &tables.specForUID(UID);
216
217 if (!Rec->isSubClassOf("X86Inst")) {
218 ShouldBeEmitted = false;
219 return;
220 }
221
222 Prefix = byteFromRec(Rec, "Prefix");
223 Opcode = byteFromRec(Rec, "Opcode");
224 Form = byteFromRec(Rec, "FormBits");
225 SegOvr = byteFromRec(Rec, "SegOvrBits");
226
227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
228 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
229 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
230 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
231 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
232 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
233 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
234 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
235 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
236 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
237 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
238
239 Name = Rec->getName();
240 AsmString = Rec->getValueAsString("AsmString");
241
242 Operands = &insn.Operands.OperandList;
243
244 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
245 (Name.find("CRC32") != Name.npos);
246 HasFROperands = hasFROperands();
247 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
248
249 // Check for 64-bit inst which does not require REX
250 Is32Bit = false;
251 Is64Bit = false;
252 // FIXME: Is there some better way to check for In64BitMode?
253 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
254 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
255 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
256 Is32Bit = true;
257 break;
258 }
259 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
260 Is64Bit = true;
261 break;
262 }
263 }
264 // FIXME: These instructions aren't marked as 64-bit in any way
265 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
266 Rec->getName() == "MASKMOVDQU64" ||
267 Rec->getName() == "POPFS64" ||
268 Rec->getName() == "POPGS64" ||
269 Rec->getName() == "PUSHFS64" ||
270 Rec->getName() == "PUSHGS64" ||
271 Rec->getName() == "REX64_PREFIX" ||
272 Rec->getName().find("MOV64") != Name.npos ||
273 Rec->getName().find("PUSH64") != Name.npos ||
274 Rec->getName().find("POP64") != Name.npos;
275
276 ShouldBeEmitted = true;
277 }
278
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)279 void RecognizableInstr::processInstr(DisassemblerTables &tables,
280 const CodeGenInstruction &insn,
281 InstrUID uid)
282 {
283 // Ignore "asm parser only" instructions.
284 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
285 return;
286
287 RecognizableInstr recogInstr(tables, insn, uid);
288
289 recogInstr.emitInstructionSpecifier(tables);
290
291 if (recogInstr.shouldBeEmitted())
292 recogInstr.emitDecodePath(tables);
293 }
294
insnContext() const295 InstructionContext RecognizableInstr::insnContext() const {
296 InstructionContext insnContext;
297
298 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
299 if (HasVEX_LPrefix && HasVEX_WPrefix) {
300 if (HasOpSizePrefix)
301 insnContext = IC_VEX_L_W_OPSIZE;
302 else
303 llvm_unreachable("Don't support VEX.L and VEX.W together");
304 } else if (HasOpSizePrefix && HasVEX_LPrefix)
305 insnContext = IC_VEX_L_OPSIZE;
306 else if (HasOpSizePrefix && HasVEX_WPrefix)
307 insnContext = IC_VEX_W_OPSIZE;
308 else if (HasOpSizePrefix)
309 insnContext = IC_VEX_OPSIZE;
310 else if (HasVEX_LPrefix &&
311 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
312 insnContext = IC_VEX_L_XS;
313 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
314 Prefix == X86Local::T8XD ||
315 Prefix == X86Local::TAXD))
316 insnContext = IC_VEX_L_XD;
317 else if (HasVEX_WPrefix &&
318 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
319 insnContext = IC_VEX_W_XS;
320 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
321 Prefix == X86Local::T8XD ||
322 Prefix == X86Local::TAXD))
323 insnContext = IC_VEX_W_XD;
324 else if (HasVEX_WPrefix)
325 insnContext = IC_VEX_W;
326 else if (HasVEX_LPrefix)
327 insnContext = IC_VEX_L;
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = IC_VEX_XD;
331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332 insnContext = IC_VEX_XS;
333 else
334 insnContext = IC_VEX;
335 } else if (Is64Bit || HasREX_WPrefix) {
336 if (HasREX_WPrefix && HasOpSizePrefix)
337 insnContext = IC_64BIT_REXW_OPSIZE;
338 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
339 Prefix == X86Local::T8XD ||
340 Prefix == X86Local::TAXD))
341 insnContext = IC_64BIT_XD_OPSIZE;
342 else if (HasOpSizePrefix &&
343 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
344 insnContext = IC_64BIT_XS_OPSIZE;
345 else if (HasOpSizePrefix)
346 insnContext = IC_64BIT_OPSIZE;
347 else if (HasAdSizePrefix)
348 insnContext = IC_64BIT_ADSIZE;
349 else if (HasREX_WPrefix &&
350 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
351 insnContext = IC_64BIT_REXW_XS;
352 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
353 Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD))
355 insnContext = IC_64BIT_REXW_XD;
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = IC_64BIT_XD;
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = IC_64BIT_XS;
361 else if (HasREX_WPrefix)
362 insnContext = IC_64BIT_REXW;
363 else
364 insnContext = IC_64BIT;
365 } else {
366 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
367 Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD))
369 insnContext = IC_XD_OPSIZE;
370 else if (HasOpSizePrefix &&
371 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
372 insnContext = IC_XS_OPSIZE;
373 else if (HasOpSizePrefix)
374 insnContext = IC_OPSIZE;
375 else if (HasAdSizePrefix)
376 insnContext = IC_ADSIZE;
377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378 Prefix == X86Local::TAXD)
379 insnContext = IC_XD;
380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
381 Prefix == X86Local::REP)
382 insnContext = IC_XS;
383 else
384 insnContext = IC;
385 }
386
387 return insnContext;
388 }
389
filter() const390 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
391 ///////////////////
392 // FILTER_STRONG
393 //
394
395 // Filter out intrinsics
396
397 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
398
399 if (Form == X86Local::Pseudo ||
400 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
401 return FILTER_STRONG;
402
403
404 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
405 // printed as a separate "instruction".
406
407 if (Name.find("_Int") != Name.npos ||
408 Name.find("Int_") != Name.npos)
409 return FILTER_STRONG;
410
411 // Filter out instructions with segment override prefixes.
412 // They're too messy to handle now and we'll special case them if needed.
413
414 if (SegOvr)
415 return FILTER_STRONG;
416
417
418 /////////////////
419 // FILTER_WEAK
420 //
421
422
423 // Filter out instructions with a LOCK prefix;
424 // prefer forms that do not have the prefix
425 if (HasLockPrefix)
426 return FILTER_WEAK;
427
428 // Filter out alternate forms of AVX instructions
429 if (Name.find("_alt") != Name.npos ||
430 Name.find("XrYr") != Name.npos ||
431 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
432 Name.find("_64mr") != Name.npos ||
433 Name.find("Xrr") != Name.npos ||
434 Name.find("rr64") != Name.npos)
435 return FILTER_WEAK;
436
437 // Special cases.
438
439 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
440 return FILTER_WEAK;
441 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
442 return FILTER_WEAK;
443
444 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
445 return FILTER_WEAK;
446 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
447 return FILTER_WEAK;
448 if (Name.find("Fs") != Name.npos)
449 return FILTER_WEAK;
450 if (Name == "PUSH64i16" ||
451 Name == "MOVPQI2QImr" ||
452 Name == "VMOVPQI2QImr" ||
453 Name == "MMX_MOVD64rrv164" ||
454 Name == "MOV64ri64i32" ||
455 Name == "VMASKMOVDQU64" ||
456 Name == "VEXTRACTPSrr64" ||
457 Name == "VMOVQd64rr" ||
458 Name == "VMOVQs64rr")
459 return FILTER_WEAK;
460
461 if (HasFROperands && Name.find("MOV") != Name.npos &&
462 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
463 (Name.find("to") != Name.npos)))
464 return FILTER_STRONG;
465
466 return FILTER_NORMAL;
467 }
468
hasFROperands() const469 bool RecognizableInstr::hasFROperands() const {
470 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
471 unsigned numOperands = OperandList.size();
472
473 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
474 const std::string &recName = OperandList[operandIndex].Rec->getName();
475
476 if (recName.find("FR") != recName.npos)
477 return true;
478 }
479 return false;
480 }
481
has256BitOperands() const482 bool RecognizableInstr::has256BitOperands() const {
483 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
484 unsigned numOperands = OperandList.size();
485
486 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
487 const std::string &recName = OperandList[operandIndex].Rec->getName();
488
489 if (!recName.compare("VR256")) {
490 return true;
491 }
492 }
493 return false;
494 }
495
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned & numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,bool hasOpSizePrefix))496 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
497 unsigned &physicalOperandIndex,
498 unsigned &numPhysicalOperands,
499 const unsigned *operandMapping,
500 OperandEncoding (*encodingFromString)
501 (const std::string&,
502 bool hasOpSizePrefix)) {
503 if (optional) {
504 if (physicalOperandIndex >= numPhysicalOperands)
505 return;
506 } else {
507 assert(physicalOperandIndex < numPhysicalOperands);
508 }
509
510 while (operandMapping[operandIndex] != operandIndex) {
511 Spec->operands[operandIndex].encoding = ENCODING_DUP;
512 Spec->operands[operandIndex].type =
513 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
514 ++operandIndex;
515 }
516
517 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
518
519 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
520 HasOpSizePrefix);
521 Spec->operands[operandIndex].type = typeFromString(typeName,
522 IsSSE,
523 HasREX_WPrefix,
524 HasOpSizePrefix);
525
526 ++operandIndex;
527 ++physicalOperandIndex;
528 }
529
emitInstructionSpecifier(DisassemblerTables & tables)530 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
531 Spec->name = Name;
532
533 if (!ShouldBeEmitted)
534 return;
535
536 switch (filter()) {
537 case FILTER_WEAK:
538 Spec->filtered = true;
539 break;
540 case FILTER_STRONG:
541 ShouldBeEmitted = false;
542 return;
543 case FILTER_NORMAL:
544 break;
545 }
546
547 Spec->insnContext = insnContext();
548
549 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
550
551 unsigned numOperands = OperandList.size();
552 unsigned numPhysicalOperands = 0;
553
554 // operandMapping maps from operands in OperandList to their originals.
555 // If operandMapping[i] != i, then the entry is a duplicate.
556 unsigned operandMapping[X86_MAX_OPERANDS];
557 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
558
559 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
560 if (OperandList[operandIndex].Constraints.size()) {
561 const CGIOperandList::ConstraintInfo &Constraint =
562 OperandList[operandIndex].Constraints[0];
563 if (Constraint.isTied()) {
564 operandMapping[operandIndex] = operandIndex;
565 operandMapping[Constraint.getTiedOperand()] = operandIndex;
566 } else {
567 ++numPhysicalOperands;
568 operandMapping[operandIndex] = operandIndex;
569 }
570 } else {
571 ++numPhysicalOperands;
572 operandMapping[operandIndex] = operandIndex;
573 }
574 }
575
576 #define HANDLE_OPERAND(class) \
577 handleOperand(false, \
578 operandIndex, \
579 physicalOperandIndex, \
580 numPhysicalOperands, \
581 operandMapping, \
582 class##EncodingFromString);
583
584 #define HANDLE_OPTIONAL(class) \
585 handleOperand(true, \
586 operandIndex, \
587 physicalOperandIndex, \
588 numPhysicalOperands, \
589 operandMapping, \
590 class##EncodingFromString);
591
592 // operandIndex should always be < numOperands
593 unsigned operandIndex = 0;
594 // physicalOperandIndex should always be < numPhysicalOperands
595 unsigned physicalOperandIndex = 0;
596
597 switch (Form) {
598 case X86Local::RawFrm:
599 // Operand 1 (optional) is an address or immediate.
600 // Operand 2 (optional) is an immediate.
601 assert(numPhysicalOperands <= 2 &&
602 "Unexpected number of operands for RawFrm");
603 HANDLE_OPTIONAL(relocation)
604 HANDLE_OPTIONAL(immediate)
605 break;
606 case X86Local::AddRegFrm:
607 // Operand 1 is added to the opcode.
608 // Operand 2 (optional) is an address.
609 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
610 "Unexpected number of operands for AddRegFrm");
611 HANDLE_OPERAND(opcodeModifier)
612 HANDLE_OPTIONAL(relocation)
613 break;
614 case X86Local::MRMDestReg:
615 // Operand 1 is a register operand in the R/M field.
616 // Operand 2 is a register operand in the Reg/Opcode field.
617 // - In AVX, there is a register operand in the VEX.vvvv field here -
618 // Operand 3 (optional) is an immediate.
619 if (HasVEX_4VPrefix)
620 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
621 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
622 else
623 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
624 "Unexpected number of operands for MRMDestRegFrm");
625
626 HANDLE_OPERAND(rmRegister)
627
628 if (HasVEX_4VPrefix)
629 // FIXME: In AVX, the register below becomes the one encoded
630 // in ModRMVEX and the one above the one in the VEX.VVVV field
631 HANDLE_OPERAND(vvvvRegister)
632
633 HANDLE_OPERAND(roRegister)
634 HANDLE_OPTIONAL(immediate)
635 break;
636 case X86Local::MRMDestMem:
637 // Operand 1 is a memory operand (possibly SIB-extended)
638 // Operand 2 is a register operand in the Reg/Opcode field.
639 // - In AVX, there is a register operand in the VEX.vvvv field here -
640 // Operand 3 (optional) is an immediate.
641 if (HasVEX_4VPrefix)
642 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
643 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
644 else
645 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
646 "Unexpected number of operands for MRMDestMemFrm");
647 HANDLE_OPERAND(memory)
648
649 if (HasVEX_4VPrefix)
650 // FIXME: In AVX, the register below becomes the one encoded
651 // in ModRMVEX and the one above the one in the VEX.VVVV field
652 HANDLE_OPERAND(vvvvRegister)
653
654 HANDLE_OPERAND(roRegister)
655 HANDLE_OPTIONAL(immediate)
656 break;
657 case X86Local::MRMSrcReg:
658 // Operand 1 is a register operand in the Reg/Opcode field.
659 // Operand 2 is a register operand in the R/M field.
660 // - In AVX, there is a register operand in the VEX.vvvv field here -
661 // Operand 3 (optional) is an immediate.
662 // Operand 4 (optional) is an immediate.
663
664 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
665 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
666 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
667 else
668 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
669 "Unexpected number of operands for MRMSrcRegFrm");
670
671 HANDLE_OPERAND(roRegister)
672
673 if (HasVEX_4VPrefix)
674 // FIXME: In AVX, the register below becomes the one encoded
675 // in ModRMVEX and the one above the one in the VEX.VVVV field
676 HANDLE_OPERAND(vvvvRegister)
677
678 if (HasMemOp4Prefix)
679 HANDLE_OPERAND(immediate)
680
681 HANDLE_OPERAND(rmRegister)
682
683 if (HasVEX_4VOp3Prefix)
684 HANDLE_OPERAND(vvvvRegister)
685
686 if (!HasMemOp4Prefix)
687 HANDLE_OPTIONAL(immediate)
688 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
689 HANDLE_OPTIONAL(immediate)
690 break;
691 case X86Local::MRMSrcMem:
692 // Operand 1 is a register operand in the Reg/Opcode field.
693 // Operand 2 is a memory operand (possibly SIB-extended)
694 // - In AVX, there is a register operand in the VEX.vvvv field here -
695 // Operand 3 (optional) is an immediate.
696
697 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
698 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
699 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
700 else
701 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
702 "Unexpected number of operands for MRMSrcMemFrm");
703
704 HANDLE_OPERAND(roRegister)
705
706 if (HasVEX_4VPrefix)
707 // FIXME: In AVX, the register below becomes the one encoded
708 // in ModRMVEX and the one above the one in the VEX.VVVV field
709 HANDLE_OPERAND(vvvvRegister)
710
711 if (HasMemOp4Prefix)
712 HANDLE_OPERAND(immediate)
713
714 HANDLE_OPERAND(memory)
715
716 if (HasVEX_4VOp3Prefix)
717 HANDLE_OPERAND(vvvvRegister)
718
719 if (!HasMemOp4Prefix)
720 HANDLE_OPTIONAL(immediate)
721 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
722 break;
723 case X86Local::MRM0r:
724 case X86Local::MRM1r:
725 case X86Local::MRM2r:
726 case X86Local::MRM3r:
727 case X86Local::MRM4r:
728 case X86Local::MRM5r:
729 case X86Local::MRM6r:
730 case X86Local::MRM7r:
731 // Operand 1 is a register operand in the R/M field.
732 // Operand 2 (optional) is an immediate or relocation.
733 // Operand 3 (optional) is an immediate.
734 if (HasVEX_4VPrefix)
735 assert(numPhysicalOperands <= 3 &&
736 "Unexpected number of operands for MRMnRFrm with VEX_4V");
737 else
738 assert(numPhysicalOperands <= 3 &&
739 "Unexpected number of operands for MRMnRFrm");
740 if (HasVEX_4VPrefix)
741 HANDLE_OPERAND(vvvvRegister)
742 HANDLE_OPTIONAL(rmRegister)
743 HANDLE_OPTIONAL(relocation)
744 HANDLE_OPTIONAL(immediate)
745 break;
746 case X86Local::MRM0m:
747 case X86Local::MRM1m:
748 case X86Local::MRM2m:
749 case X86Local::MRM3m:
750 case X86Local::MRM4m:
751 case X86Local::MRM5m:
752 case X86Local::MRM6m:
753 case X86Local::MRM7m:
754 // Operand 1 is a memory operand (possibly SIB-extended)
755 // Operand 2 (optional) is an immediate or relocation.
756 if (HasVEX_4VPrefix)
757 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
758 "Unexpected number of operands for MRMnMFrm");
759 else
760 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
761 "Unexpected number of operands for MRMnMFrm");
762 if (HasVEX_4VPrefix)
763 HANDLE_OPERAND(vvvvRegister)
764 HANDLE_OPERAND(memory)
765 HANDLE_OPTIONAL(relocation)
766 break;
767 case X86Local::RawFrmImm8:
768 // operand 1 is a 16-bit immediate
769 // operand 2 is an 8-bit immediate
770 assert(numPhysicalOperands == 2 &&
771 "Unexpected number of operands for X86Local::RawFrmImm8");
772 HANDLE_OPERAND(immediate)
773 HANDLE_OPERAND(immediate)
774 break;
775 case X86Local::RawFrmImm16:
776 // operand 1 is a 16-bit immediate
777 // operand 2 is a 16-bit immediate
778 HANDLE_OPERAND(immediate)
779 HANDLE_OPERAND(immediate)
780 break;
781 case X86Local::MRMInitReg:
782 // Ignored.
783 break;
784 }
785
786 #undef HANDLE_OPERAND
787 #undef HANDLE_OPTIONAL
788 }
789
emitDecodePath(DisassemblerTables & tables) const790 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
791 // Special cases where the LLVM tables are not complete
792
793 #define MAP(from, to) \
794 case X86Local::MRM_##from: \
795 filter = new ExactFilter(0x##from); \
796 break;
797
798 OpcodeType opcodeType = (OpcodeType)-1;
799
800 ModRMFilter* filter = NULL;
801 uint8_t opcodeToSet = 0;
802
803 switch (Prefix) {
804 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
805 case X86Local::XD:
806 case X86Local::XS:
807 case X86Local::TB:
808 opcodeType = TWOBYTE;
809
810 switch (Opcode) {
811 default:
812 if (needsModRMForDecode(Form))
813 filter = new ModFilter(isRegFormat(Form));
814 else
815 filter = new DumbFilter();
816 break;
817 #define EXTENSION_TABLE(n) case 0x##n:
818 TWO_BYTE_EXTENSION_TABLES
819 #undef EXTENSION_TABLE
820 switch (Form) {
821 default:
822 llvm_unreachable("Unhandled two-byte extended opcode");
823 case X86Local::MRM0r:
824 case X86Local::MRM1r:
825 case X86Local::MRM2r:
826 case X86Local::MRM3r:
827 case X86Local::MRM4r:
828 case X86Local::MRM5r:
829 case X86Local::MRM6r:
830 case X86Local::MRM7r:
831 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
832 break;
833 case X86Local::MRM0m:
834 case X86Local::MRM1m:
835 case X86Local::MRM2m:
836 case X86Local::MRM3m:
837 case X86Local::MRM4m:
838 case X86Local::MRM5m:
839 case X86Local::MRM6m:
840 case X86Local::MRM7m:
841 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
842 break;
843 MRM_MAPPING
844 } // switch (Form)
845 break;
846 } // switch (Opcode)
847 opcodeToSet = Opcode;
848 break;
849 case X86Local::T8:
850 case X86Local::T8XD:
851 case X86Local::T8XS:
852 opcodeType = THREEBYTE_38;
853 switch (Opcode) {
854 default:
855 if (needsModRMForDecode(Form))
856 filter = new ModFilter(isRegFormat(Form));
857 else
858 filter = new DumbFilter();
859 break;
860 #define EXTENSION_TABLE(n) case 0x##n:
861 THREE_BYTE_38_EXTENSION_TABLES
862 #undef EXTENSION_TABLE
863 switch (Form) {
864 default:
865 llvm_unreachable("Unhandled two-byte extended opcode");
866 case X86Local::MRM0r:
867 case X86Local::MRM1r:
868 case X86Local::MRM2r:
869 case X86Local::MRM3r:
870 case X86Local::MRM4r:
871 case X86Local::MRM5r:
872 case X86Local::MRM6r:
873 case X86Local::MRM7r:
874 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
875 break;
876 case X86Local::MRM0m:
877 case X86Local::MRM1m:
878 case X86Local::MRM2m:
879 case X86Local::MRM3m:
880 case X86Local::MRM4m:
881 case X86Local::MRM5m:
882 case X86Local::MRM6m:
883 case X86Local::MRM7m:
884 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
885 break;
886 MRM_MAPPING
887 } // switch (Form)
888 break;
889 } // switch (Opcode)
890 opcodeToSet = Opcode;
891 break;
892 case X86Local::P_TA:
893 case X86Local::TAXD:
894 opcodeType = THREEBYTE_3A;
895 if (needsModRMForDecode(Form))
896 filter = new ModFilter(isRegFormat(Form));
897 else
898 filter = new DumbFilter();
899 opcodeToSet = Opcode;
900 break;
901 case X86Local::A6:
902 opcodeType = THREEBYTE_A6;
903 if (needsModRMForDecode(Form))
904 filter = new ModFilter(isRegFormat(Form));
905 else
906 filter = new DumbFilter();
907 opcodeToSet = Opcode;
908 break;
909 case X86Local::A7:
910 opcodeType = THREEBYTE_A7;
911 if (needsModRMForDecode(Form))
912 filter = new ModFilter(isRegFormat(Form));
913 else
914 filter = new DumbFilter();
915 opcodeToSet = Opcode;
916 break;
917 case X86Local::D8:
918 case X86Local::D9:
919 case X86Local::DA:
920 case X86Local::DB:
921 case X86Local::DC:
922 case X86Local::DD:
923 case X86Local::DE:
924 case X86Local::DF:
925 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
926 opcodeType = ONEBYTE;
927 if (Form == X86Local::AddRegFrm) {
928 Spec->modifierType = MODIFIER_MODRM;
929 Spec->modifierBase = Opcode;
930 filter = new AddRegEscapeFilter(Opcode);
931 } else {
932 filter = new EscapeFilter(true, Opcode);
933 }
934 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
935 break;
936 case X86Local::REP:
937 default:
938 opcodeType = ONEBYTE;
939 switch (Opcode) {
940 #define EXTENSION_TABLE(n) case 0x##n:
941 ONE_BYTE_EXTENSION_TABLES
942 #undef EXTENSION_TABLE
943 switch (Form) {
944 default:
945 llvm_unreachable("Fell through the cracks of a single-byte "
946 "extended opcode");
947 case X86Local::MRM0r:
948 case X86Local::MRM1r:
949 case X86Local::MRM2r:
950 case X86Local::MRM3r:
951 case X86Local::MRM4r:
952 case X86Local::MRM5r:
953 case X86Local::MRM6r:
954 case X86Local::MRM7r:
955 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
956 break;
957 case X86Local::MRM0m:
958 case X86Local::MRM1m:
959 case X86Local::MRM2m:
960 case X86Local::MRM3m:
961 case X86Local::MRM4m:
962 case X86Local::MRM5m:
963 case X86Local::MRM6m:
964 case X86Local::MRM7m:
965 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
966 break;
967 MRM_MAPPING
968 } // switch (Form)
969 break;
970 case 0xd8:
971 case 0xd9:
972 case 0xda:
973 case 0xdb:
974 case 0xdc:
975 case 0xdd:
976 case 0xde:
977 case 0xdf:
978 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
979 break;
980 default:
981 if (needsModRMForDecode(Form))
982 filter = new ModFilter(isRegFormat(Form));
983 else
984 filter = new DumbFilter();
985 break;
986 } // switch (Opcode)
987 opcodeToSet = Opcode;
988 } // switch (Prefix)
989
990 assert(opcodeType != (OpcodeType)-1 &&
991 "Opcode type not set");
992 assert(filter && "Filter not set");
993
994 if (Form == X86Local::AddRegFrm) {
995 if(Spec->modifierType != MODIFIER_MODRM) {
996 assert(opcodeToSet < 0xf9 &&
997 "Not enough room for all ADDREG_FRM operands");
998
999 uint8_t currentOpcode;
1000
1001 for (currentOpcode = opcodeToSet;
1002 currentOpcode < opcodeToSet + 8;
1003 ++currentOpcode)
1004 tables.setTableFields(opcodeType,
1005 insnContext(),
1006 currentOpcode,
1007 *filter,
1008 UID, Is32Bit, IgnoresVEX_L);
1009
1010 Spec->modifierType = MODIFIER_OPCODE;
1011 Spec->modifierBase = opcodeToSet;
1012 } else {
1013 // modifierBase was set where MODIFIER_MODRM was set
1014 tables.setTableFields(opcodeType,
1015 insnContext(),
1016 opcodeToSet,
1017 *filter,
1018 UID, Is32Bit, IgnoresVEX_L);
1019 }
1020 } else {
1021 tables.setTableFields(opcodeType,
1022 insnContext(),
1023 opcodeToSet,
1024 *filter,
1025 UID, Is32Bit, IgnoresVEX_L);
1026
1027 Spec->modifierType = MODIFIER_NONE;
1028 Spec->modifierBase = opcodeToSet;
1029 }
1030
1031 delete filter;
1032
1033 #undef MAP
1034 }
1035
1036 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool isSSE,bool hasREX_WPrefix,bool hasOpSizePrefix)1037 OperandType RecognizableInstr::typeFromString(const std::string &s,
1038 bool isSSE,
1039 bool hasREX_WPrefix,
1040 bool hasOpSizePrefix) {
1041 if (isSSE) {
1042 // For SSE instructions, we ignore the OpSize prefix and force operand
1043 // sizes.
1044 TYPE("GR16", TYPE_R16)
1045 TYPE("GR32", TYPE_R32)
1046 TYPE("GR64", TYPE_R64)
1047 }
1048 if(hasREX_WPrefix) {
1049 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1050 // is special.
1051 TYPE("GR32", TYPE_R32)
1052 }
1053 if(!hasOpSizePrefix) {
1054 // For instructions without an OpSize prefix, a declared 16-bit register or
1055 // immediate encoding is special.
1056 TYPE("GR16", TYPE_R16)
1057 TYPE("i16imm", TYPE_IMM16)
1058 }
1059 TYPE("i16mem", TYPE_Mv)
1060 TYPE("i16imm", TYPE_IMMv)
1061 TYPE("i16i8imm", TYPE_IMMv)
1062 TYPE("GR16", TYPE_Rv)
1063 TYPE("i32mem", TYPE_Mv)
1064 TYPE("i32imm", TYPE_IMMv)
1065 TYPE("i32i8imm", TYPE_IMM32)
1066 TYPE("u32u8imm", TYPE_IMM32)
1067 TYPE("GR32", TYPE_Rv)
1068 TYPE("i64mem", TYPE_Mv)
1069 TYPE("i64i32imm", TYPE_IMM64)
1070 TYPE("i64i8imm", TYPE_IMM64)
1071 TYPE("GR64", TYPE_R64)
1072 TYPE("i8mem", TYPE_M8)
1073 TYPE("i8imm", TYPE_IMM8)
1074 TYPE("GR8", TYPE_R8)
1075 TYPE("VR128", TYPE_XMM128)
1076 TYPE("f128mem", TYPE_M128)
1077 TYPE("f256mem", TYPE_M256)
1078 TYPE("FR64", TYPE_XMM64)
1079 TYPE("f64mem", TYPE_M64FP)
1080 TYPE("sdmem", TYPE_M64FP)
1081 TYPE("FR32", TYPE_XMM32)
1082 TYPE("f32mem", TYPE_M32FP)
1083 TYPE("ssmem", TYPE_M32FP)
1084 TYPE("RST", TYPE_ST)
1085 TYPE("i128mem", TYPE_M128)
1086 TYPE("i256mem", TYPE_M256)
1087 TYPE("i64i32imm_pcrel", TYPE_REL64)
1088 TYPE("i16imm_pcrel", TYPE_REL16)
1089 TYPE("i32imm_pcrel", TYPE_REL32)
1090 TYPE("SSECC", TYPE_IMM3)
1091 TYPE("AVXCC", TYPE_IMM5)
1092 TYPE("brtarget", TYPE_RELv)
1093 TYPE("uncondbrtarget", TYPE_RELv)
1094 TYPE("brtarget8", TYPE_REL8)
1095 TYPE("f80mem", TYPE_M80FP)
1096 TYPE("lea32mem", TYPE_LEA)
1097 TYPE("lea64_32mem", TYPE_LEA)
1098 TYPE("lea64mem", TYPE_LEA)
1099 TYPE("VR64", TYPE_MM64)
1100 TYPE("i64imm", TYPE_IMMv)
1101 TYPE("opaque32mem", TYPE_M1616)
1102 TYPE("opaque48mem", TYPE_M1632)
1103 TYPE("opaque80mem", TYPE_M1664)
1104 TYPE("opaque512mem", TYPE_M512)
1105 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1106 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1107 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1108 TYPE("offset8", TYPE_MOFFS8)
1109 TYPE("offset16", TYPE_MOFFS16)
1110 TYPE("offset32", TYPE_MOFFS32)
1111 TYPE("offset64", TYPE_MOFFS64)
1112 TYPE("VR256", TYPE_XMM256)
1113 TYPE("GR16_NOAX", TYPE_Rv)
1114 TYPE("GR32_NOAX", TYPE_Rv)
1115 TYPE("GR64_NOAX", TYPE_R64)
1116 TYPE("vx32mem", TYPE_M32)
1117 TYPE("vy32mem", TYPE_M32)
1118 TYPE("vx64mem", TYPE_M64)
1119 TYPE("vy64mem", TYPE_M64)
1120 errs() << "Unhandled type string " << s << "\n";
1121 llvm_unreachable("Unhandled type string");
1122 }
1123 #undef TYPE
1124
1125 #define ENCODING(str, encoding) if (s == str) return encoding;
immediateEncodingFromString(const std::string & s,bool hasOpSizePrefix)1126 OperandEncoding RecognizableInstr::immediateEncodingFromString
1127 (const std::string &s,
1128 bool hasOpSizePrefix) {
1129 if(!hasOpSizePrefix) {
1130 // For instructions without an OpSize prefix, a declared 16-bit register or
1131 // immediate encoding is special.
1132 ENCODING("i16imm", ENCODING_IW)
1133 }
1134 ENCODING("i32i8imm", ENCODING_IB)
1135 ENCODING("u32u8imm", ENCODING_IB)
1136 ENCODING("SSECC", ENCODING_IB)
1137 ENCODING("AVXCC", ENCODING_IB)
1138 ENCODING("i16imm", ENCODING_Iv)
1139 ENCODING("i16i8imm", ENCODING_IB)
1140 ENCODING("i32imm", ENCODING_Iv)
1141 ENCODING("i64i32imm", ENCODING_ID)
1142 ENCODING("i64i8imm", ENCODING_IB)
1143 ENCODING("i8imm", ENCODING_IB)
1144 // This is not a typo. Instructions like BLENDVPD put
1145 // register IDs in 8-bit immediates nowadays.
1146 ENCODING("VR256", ENCODING_IB)
1147 ENCODING("VR128", ENCODING_IB)
1148 ENCODING("FR32", ENCODING_IB)
1149 ENCODING("FR64", ENCODING_IB)
1150 errs() << "Unhandled immediate encoding " << s << "\n";
1151 llvm_unreachable("Unhandled immediate encoding");
1152 }
1153
rmRegisterEncodingFromString(const std::string & s,bool hasOpSizePrefix)1154 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1155 (const std::string &s,
1156 bool hasOpSizePrefix) {
1157 ENCODING("GR16", ENCODING_RM)
1158 ENCODING("GR32", ENCODING_RM)
1159 ENCODING("GR64", ENCODING_RM)
1160 ENCODING("GR8", ENCODING_RM)
1161 ENCODING("VR128", ENCODING_RM)
1162 ENCODING("FR64", ENCODING_RM)
1163 ENCODING("FR32", ENCODING_RM)
1164 ENCODING("VR64", ENCODING_RM)
1165 ENCODING("VR256", ENCODING_RM)
1166 errs() << "Unhandled R/M register encoding " << s << "\n";
1167 llvm_unreachable("Unhandled R/M register encoding");
1168 }
1169
roRegisterEncodingFromString(const std::string & s,bool hasOpSizePrefix)1170 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1171 (const std::string &s,
1172 bool hasOpSizePrefix) {
1173 ENCODING("GR16", ENCODING_REG)
1174 ENCODING("GR32", ENCODING_REG)
1175 ENCODING("GR64", ENCODING_REG)
1176 ENCODING("GR8", ENCODING_REG)
1177 ENCODING("VR128", ENCODING_REG)
1178 ENCODING("FR64", ENCODING_REG)
1179 ENCODING("FR32", ENCODING_REG)
1180 ENCODING("VR64", ENCODING_REG)
1181 ENCODING("SEGMENT_REG", ENCODING_REG)
1182 ENCODING("DEBUG_REG", ENCODING_REG)
1183 ENCODING("CONTROL_REG", ENCODING_REG)
1184 ENCODING("VR256", ENCODING_REG)
1185 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1186 llvm_unreachable("Unhandled reg/opcode register encoding");
1187 }
1188
vvvvRegisterEncodingFromString(const std::string & s,bool hasOpSizePrefix)1189 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1190 (const std::string &s,
1191 bool hasOpSizePrefix) {
1192 ENCODING("GR32", ENCODING_VVVV)
1193 ENCODING("GR64", ENCODING_VVVV)
1194 ENCODING("FR32", ENCODING_VVVV)
1195 ENCODING("FR64", ENCODING_VVVV)
1196 ENCODING("VR128", ENCODING_VVVV)
1197 ENCODING("VR256", ENCODING_VVVV)
1198 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1199 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1200 }
1201
memoryEncodingFromString(const std::string & s,bool hasOpSizePrefix)1202 OperandEncoding RecognizableInstr::memoryEncodingFromString
1203 (const std::string &s,
1204 bool hasOpSizePrefix) {
1205 ENCODING("i16mem", ENCODING_RM)
1206 ENCODING("i32mem", ENCODING_RM)
1207 ENCODING("i64mem", ENCODING_RM)
1208 ENCODING("i8mem", ENCODING_RM)
1209 ENCODING("ssmem", ENCODING_RM)
1210 ENCODING("sdmem", ENCODING_RM)
1211 ENCODING("f128mem", ENCODING_RM)
1212 ENCODING("f256mem", ENCODING_RM)
1213 ENCODING("f64mem", ENCODING_RM)
1214 ENCODING("f32mem", ENCODING_RM)
1215 ENCODING("i128mem", ENCODING_RM)
1216 ENCODING("i256mem", ENCODING_RM)
1217 ENCODING("f80mem", ENCODING_RM)
1218 ENCODING("lea32mem", ENCODING_RM)
1219 ENCODING("lea64_32mem", ENCODING_RM)
1220 ENCODING("lea64mem", ENCODING_RM)
1221 ENCODING("opaque32mem", ENCODING_RM)
1222 ENCODING("opaque48mem", ENCODING_RM)
1223 ENCODING("opaque80mem", ENCODING_RM)
1224 ENCODING("opaque512mem", ENCODING_RM)
1225 ENCODING("vx32mem", ENCODING_RM)
1226 ENCODING("vy32mem", ENCODING_RM)
1227 ENCODING("vx64mem", ENCODING_RM)
1228 ENCODING("vy64mem", ENCODING_RM)
1229 errs() << "Unhandled memory encoding " << s << "\n";
1230 llvm_unreachable("Unhandled memory encoding");
1231 }
1232
relocationEncodingFromString(const std::string & s,bool hasOpSizePrefix)1233 OperandEncoding RecognizableInstr::relocationEncodingFromString
1234 (const std::string &s,
1235 bool hasOpSizePrefix) {
1236 if(!hasOpSizePrefix) {
1237 // For instructions without an OpSize prefix, a declared 16-bit register or
1238 // immediate encoding is special.
1239 ENCODING("i16imm", ENCODING_IW)
1240 }
1241 ENCODING("i16imm", ENCODING_Iv)
1242 ENCODING("i16i8imm", ENCODING_IB)
1243 ENCODING("i32imm", ENCODING_Iv)
1244 ENCODING("i32i8imm", ENCODING_IB)
1245 ENCODING("i64i32imm", ENCODING_ID)
1246 ENCODING("i64i8imm", ENCODING_IB)
1247 ENCODING("i8imm", ENCODING_IB)
1248 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1249 ENCODING("i16imm_pcrel", ENCODING_IW)
1250 ENCODING("i32imm_pcrel", ENCODING_ID)
1251 ENCODING("brtarget", ENCODING_Iv)
1252 ENCODING("brtarget8", ENCODING_IB)
1253 ENCODING("i64imm", ENCODING_IO)
1254 ENCODING("offset8", ENCODING_Ia)
1255 ENCODING("offset16", ENCODING_Ia)
1256 ENCODING("offset32", ENCODING_Ia)
1257 ENCODING("offset64", ENCODING_Ia)
1258 errs() << "Unhandled relocation encoding " << s << "\n";
1259 llvm_unreachable("Unhandled relocation encoding");
1260 }
1261
opcodeModifierEncodingFromString(const std::string & s,bool hasOpSizePrefix)1262 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1263 (const std::string &s,
1264 bool hasOpSizePrefix) {
1265 ENCODING("RST", ENCODING_I)
1266 ENCODING("GR32", ENCODING_Rv)
1267 ENCODING("GR64", ENCODING_RO)
1268 ENCODING("GR16", ENCODING_Rv)
1269 ENCODING("GR8", ENCODING_RB)
1270 ENCODING("GR16_NOAX", ENCODING_Rv)
1271 ENCODING("GR32_NOAX", ENCODING_Rv)
1272 ENCODING("GR64_NOAX", ENCODING_RO)
1273 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1274 llvm_unreachable("Unhandled opcode modifier encoding");
1275 }
1276 #undef ENCODING
1277