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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
16 
17 #include "llvm/Target/TargetSubtargetInfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include <string>
20 
21 #define GET_SUBTARGETINFO_HEADER
22 #include "MipsGenSubtargetInfo.inc"
23 
24 namespace llvm {
25 class StringRef;
26 
27 class MipsSubtarget : public MipsGenSubtargetInfo {
28   virtual void anchor();
29 
30 public:
31   // NOTE: O64 will not be supported.
32   enum MipsABIEnum {
33     UnknownABI, O32, N32, N64, EABI
34   };
35 
36 protected:
37 
38   enum MipsArchEnum {
39     Mips32, Mips32r2, Mips64, Mips64r2
40   };
41 
42   // Mips architecture version
43   MipsArchEnum MipsArchVersion;
44 
45   // Mips supported ABIs
46   MipsABIEnum MipsABI;
47 
48   // IsLittle - The target is Little Endian
49   bool IsLittle;
50 
51   // IsSingleFloat - The target only supports single precision float
52   // point operations. This enable the target to use all 32 32-bit
53   // floating point registers instead of only using even ones.
54   bool IsSingleFloat;
55 
56   // IsFP64bit - The target processor has 64-bit floating point registers.
57   bool IsFP64bit;
58 
59   // IsFP64bit - General-purpose registers are 64 bits wide
60   bool IsGP64bit;
61 
62   // HasVFPU - Processor has a vector floating point unit.
63   bool HasVFPU;
64 
65   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
66   bool IsLinux;
67 
68   // UseSmallSection - Small section is used.
69   bool UseSmallSection;
70 
71   /// Features related to the presence of specific instructions.
72 
73   // HasSEInReg - SEB and SEH (signext in register) instructions.
74   bool HasSEInReg;
75 
76   // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
77   bool HasCondMov;
78 
79   // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
80   // instructions.
81   bool HasMulDivAdd;
82 
83   // HasMinMax - MIN and MAX instructions.
84   bool HasMinMax;
85 
86   // HasSwap - Byte and half swap instructions.
87   bool HasSwap;
88 
89   // HasBitCount - Count leading '1' and '0' bits.
90   bool HasBitCount;
91 
92   // InMips16 -- can process Mips16 instructions
93   bool InMips16Mode;
94 
95   // IsAndroid -- target is android
96   bool IsAndroid;
97 
98   InstrItineraryData InstrItins;
99 
100 public:
101   virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
102                                      AntiDepBreakMode& Mode,
103                                      RegClassVector& CriticalPathRCs) const;
104 
105   /// Only O32 and EABI supported right now.
isABI_EABI()106   bool isABI_EABI() const { return MipsABI == EABI; }
isABI_N64()107   bool isABI_N64() const { return MipsABI == N64; }
isABI_N32()108   bool isABI_N32() const { return MipsABI == N32; }
isABI_O32()109   bool isABI_O32() const { return MipsABI == O32; }
getTargetABI()110   unsigned getTargetABI() const { return MipsABI; }
111 
112   /// This constructor initializes the data members to match that
113   /// of the specified triple.
114   MipsSubtarget(const std::string &TT, const std::string &CPU,
115                 const std::string &FS, bool little, Reloc::Model RM);
116 
117   /// ParseSubtargetFeatures - Parses features string setting specified
118   /// subtarget options.  Definition of function is auto generated by tblgen.
119   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
120 
hasMips32()121   bool hasMips32() const { return MipsArchVersion >= Mips32; }
hasMips32r2()122   bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
123                                    MipsArchVersion == Mips64r2; }
hasMips64()124   bool hasMips64() const { return MipsArchVersion >= Mips64; }
hasMips64r2()125   bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
126 
hasMips32r2Or64()127   bool hasMips32r2Or64() const { return hasMips32r2() || hasMips64(); }
128 
isLittle()129   bool isLittle() const { return IsLittle; }
isFP64bit()130   bool isFP64bit() const { return IsFP64bit; }
isGP64bit()131   bool isGP64bit() const { return IsGP64bit; }
isGP32bit()132   bool isGP32bit() const { return !IsGP64bit; }
isSingleFloat()133   bool isSingleFloat() const { return IsSingleFloat; }
isNotSingleFloat()134   bool isNotSingleFloat() const { return !IsSingleFloat; }
hasVFPU()135   bool hasVFPU() const { return HasVFPU; }
inMips16Mode()136   bool inMips16Mode() const { return InMips16Mode; }
isAndroid()137   bool isAndroid() const { return IsAndroid; }
isLinux()138   bool isLinux() const { return IsLinux; }
useSmallSection()139   bool useSmallSection() const { return UseSmallSection; }
140 
hasStandardEncoding()141   bool hasStandardEncoding() const { return !inMips16Mode(); }
142 
143   /// Features related to the presence of specific instructions.
hasSEInReg()144   bool hasSEInReg()   const { return HasSEInReg; }
hasCondMov()145   bool hasCondMov()   const { return HasCondMov; }
hasMulDivAdd()146   bool hasMulDivAdd() const { return HasMulDivAdd; }
hasMinMax()147   bool hasMinMax()    const { return HasMinMax; }
hasSwap()148   bool hasSwap()      const { return HasSwap; }
hasBitCount()149   bool hasBitCount()  const { return HasBitCount; }
150 };
151 } // End llvm namespace
152 
153 #endif
154