1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef ARMBASEINFO_H
18 #define ARMBASEINFO_H
19
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22
23 namespace llvm {
24
25 // Enums corresponding to ARM condition codes
26 namespace ARMCC {
27 // The CondCodes constants map directly to the 4-bit encoding of the
28 // condition field for predicated instructions.
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
30 EQ, // Equal Equal
31 NE, // Not equal Not equal, or unordered
32 HS, // Carry set >, ==, or unordered
33 LO, // Carry clear Less than
34 MI, // Minus, negative Less than
35 PL, // Plus, positive or zero >, ==, or unordered
36 VS, // Overflow Unordered
37 VC, // No overflow Not unordered
38 HI, // Unsigned higher Greater than, or unordered
39 LS, // Unsigned lower or same Less than or equal
40 GE, // Greater than or equal Greater than or equal
41 LT, // Less than Less than, or unordered
42 GT, // Greater than Greater than
43 LE, // Less than or equal <, ==, or unordered
44 AL // Always (unconditional) Always (unconditional)
45 };
46
getOppositeCondition(CondCodes CC)47 inline static CondCodes getOppositeCondition(CondCodes CC) {
48 switch (CC) {
49 default: llvm_unreachable("Unknown condition code");
50 case EQ: return NE;
51 case NE: return EQ;
52 case HS: return LO;
53 case LO: return HS;
54 case MI: return PL;
55 case PL: return MI;
56 case VS: return VC;
57 case VC: return VS;
58 case HI: return LS;
59 case LS: return HI;
60 case GE: return LT;
61 case LT: return GE;
62 case GT: return LE;
63 case LE: return GT;
64 }
65 }
66 } // namespace ARMCC
67
ARMCondCodeToString(ARMCC::CondCodes CC)68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
69 switch (CC) {
70 case ARMCC::EQ: return "eq";
71 case ARMCC::NE: return "ne";
72 case ARMCC::HS: return "hs";
73 case ARMCC::LO: return "lo";
74 case ARMCC::MI: return "mi";
75 case ARMCC::PL: return "pl";
76 case ARMCC::VS: return "vs";
77 case ARMCC::VC: return "vc";
78 case ARMCC::HI: return "hi";
79 case ARMCC::LS: return "ls";
80 case ARMCC::GE: return "ge";
81 case ARMCC::LT: return "lt";
82 case ARMCC::GT: return "gt";
83 case ARMCC::LE: return "le";
84 case ARMCC::AL: return "al";
85 }
86 llvm_unreachable("Unknown condition code");
87 }
88
89 namespace ARM_PROC {
90 enum IMod {
91 IE = 2,
92 ID = 3
93 };
94
95 enum IFlags {
96 F = 1,
97 I = 2,
98 A = 4
99 };
100
IFlagsToString(unsigned val)101 inline static const char *IFlagsToString(unsigned val) {
102 switch (val) {
103 default: llvm_unreachable("Unknown iflags operand");
104 case F: return "f";
105 case I: return "i";
106 case A: return "a";
107 }
108 }
109
IModToString(unsigned val)110 inline static const char *IModToString(unsigned val) {
111 switch (val) {
112 default: llvm_unreachable("Unknown imod operand");
113 case IE: return "ie";
114 case ID: return "id";
115 }
116 }
117 }
118
119 namespace ARM_MB {
120 // The Memory Barrier Option constants map directly to the 4-bit encoding of
121 // the option field for memory barrier operations.
122 enum MemBOpt {
123 RESERVED_0 = 0,
124 RESERVED_1 = 1,
125 OSHST = 2,
126 OSH = 3,
127 RESERVED_4 = 4,
128 RESERVED_5 = 5,
129 NSHST = 6,
130 NSH = 7,
131 RESERVED_8 = 8,
132 RESERVED_9 = 9,
133 ISHST = 10,
134 ISH = 11,
135 RESERVED_12 = 12,
136 RESERVED_13 = 13,
137 ST = 14,
138 SY = 15
139 };
140
MemBOptToString(unsigned val)141 inline static const char *MemBOptToString(unsigned val) {
142 switch (val) {
143 default: llvm_unreachable("Unknown memory operation");
144 case SY: return "sy";
145 case ST: return "st";
146 case RESERVED_13: return "#0xd";
147 case RESERVED_12: return "#0xc";
148 case ISH: return "ish";
149 case ISHST: return "ishst";
150 case RESERVED_9: return "#0x9";
151 case RESERVED_8: return "#0x8";
152 case NSH: return "nsh";
153 case NSHST: return "nshst";
154 case RESERVED_5: return "#0x5";
155 case RESERVED_4: return "#0x4";
156 case OSH: return "osh";
157 case OSHST: return "oshst";
158 case RESERVED_1: return "#0x1";
159 case RESERVED_0: return "#0x0";
160 }
161 }
162 } // namespace ARM_MB
163
164 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
165 ///
isARMLowRegister(unsigned Reg)166 static inline bool isARMLowRegister(unsigned Reg) {
167 using namespace ARM;
168 switch (Reg) {
169 case R0: case R1: case R2: case R3:
170 case R4: case R5: case R6: case R7:
171 return true;
172 default:
173 return false;
174 }
175 }
176
177 /// ARMII - This namespace holds all of the target specific flags that
178 /// instruction info tracks.
179 ///
180 namespace ARMII {
181
182 /// ARM Index Modes
183 enum IndexMode {
184 IndexModeNone = 0,
185 IndexModePre = 1,
186 IndexModePost = 2,
187 IndexModeUpd = 3
188 };
189
190 /// ARM Addressing Modes
191 enum AddrMode {
192 AddrModeNone = 0,
193 AddrMode1 = 1,
194 AddrMode2 = 2,
195 AddrMode3 = 3,
196 AddrMode4 = 4,
197 AddrMode5 = 5,
198 AddrMode6 = 6,
199 AddrModeT1_1 = 7,
200 AddrModeT1_2 = 8,
201 AddrModeT1_4 = 9,
202 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
203 AddrModeT2_i12 = 11,
204 AddrModeT2_i8 = 12,
205 AddrModeT2_so = 13,
206 AddrModeT2_pc = 14, // +/- i12 for pc relative data
207 AddrModeT2_i8s4 = 15, // i8 * 4
208 AddrMode_i12 = 16
209 };
210
AddrModeToString(AddrMode addrmode)211 inline static const char *AddrModeToString(AddrMode addrmode) {
212 switch (addrmode) {
213 case AddrModeNone: return "AddrModeNone";
214 case AddrMode1: return "AddrMode1";
215 case AddrMode2: return "AddrMode2";
216 case AddrMode3: return "AddrMode3";
217 case AddrMode4: return "AddrMode4";
218 case AddrMode5: return "AddrMode5";
219 case AddrMode6: return "AddrMode6";
220 case AddrModeT1_1: return "AddrModeT1_1";
221 case AddrModeT1_2: return "AddrModeT1_2";
222 case AddrModeT1_4: return "AddrModeT1_4";
223 case AddrModeT1_s: return "AddrModeT1_s";
224 case AddrModeT2_i12: return "AddrModeT2_i12";
225 case AddrModeT2_i8: return "AddrModeT2_i8";
226 case AddrModeT2_so: return "AddrModeT2_so";
227 case AddrModeT2_pc: return "AddrModeT2_pc";
228 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
229 case AddrMode_i12: return "AddrMode_i12";
230 }
231 }
232
233 /// Target Operand Flag enum.
234 enum TOF {
235 //===------------------------------------------------------------------===//
236 // ARM Specific MachineOperand flags.
237
238 MO_NO_FLAG,
239
240 /// MO_LO16 - On a symbol operand, this represents a relocation containing
241 /// lower 16 bit of the address. Used only via movw instruction.
242 MO_LO16,
243
244 /// MO_HI16 - On a symbol operand, this represents a relocation containing
245 /// higher 16 bit of the address. Used only via movt instruction.
246 MO_HI16,
247
248 /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
249 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
250 /// i.e. "FOO$non_lazy_ptr".
251 /// Used only via movw instruction.
252 MO_LO16_NONLAZY,
253
254 /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
255 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
256 /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
257 MO_HI16_NONLAZY,
258
259 /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
260 /// relocation containing lower 16 bit of the PC relative address of the
261 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
262 /// Used only via movw instruction.
263 MO_LO16_NONLAZY_PIC,
264
265 /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
266 /// relocation containing lower 16 bit of the PC relative address of the
267 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
268 /// Used only via movt instruction.
269 MO_HI16_NONLAZY_PIC,
270
271 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
272 /// call operand.
273 MO_PLT
274 };
275
276 enum {
277 //===------------------------------------------------------------------===//
278 // Instruction Flags.
279
280 //===------------------------------------------------------------------===//
281 // This four-bit field describes the addressing mode used.
282 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
283
284 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
285 // and store ops only. Generic "updating" flag is used for ld/st multiple.
286 // The index mode enums are declared in ARMBaseInfo.h
287 IndexModeShift = 5,
288 IndexModeMask = 3 << IndexModeShift,
289
290 //===------------------------------------------------------------------===//
291 // Instruction encoding formats.
292 //
293 FormShift = 7,
294 FormMask = 0x3f << FormShift,
295
296 // Pseudo instructions
297 Pseudo = 0 << FormShift,
298
299 // Multiply instructions
300 MulFrm = 1 << FormShift,
301
302 // Branch instructions
303 BrFrm = 2 << FormShift,
304 BrMiscFrm = 3 << FormShift,
305
306 // Data Processing instructions
307 DPFrm = 4 << FormShift,
308 DPSoRegFrm = 5 << FormShift,
309
310 // Load and Store
311 LdFrm = 6 << FormShift,
312 StFrm = 7 << FormShift,
313 LdMiscFrm = 8 << FormShift,
314 StMiscFrm = 9 << FormShift,
315 LdStMulFrm = 10 << FormShift,
316
317 LdStExFrm = 11 << FormShift,
318
319 // Miscellaneous arithmetic instructions
320 ArithMiscFrm = 12 << FormShift,
321 SatFrm = 13 << FormShift,
322
323 // Extend instructions
324 ExtFrm = 14 << FormShift,
325
326 // VFP formats
327 VFPUnaryFrm = 15 << FormShift,
328 VFPBinaryFrm = 16 << FormShift,
329 VFPConv1Frm = 17 << FormShift,
330 VFPConv2Frm = 18 << FormShift,
331 VFPConv3Frm = 19 << FormShift,
332 VFPConv4Frm = 20 << FormShift,
333 VFPConv5Frm = 21 << FormShift,
334 VFPLdStFrm = 22 << FormShift,
335 VFPLdStMulFrm = 23 << FormShift,
336 VFPMiscFrm = 24 << FormShift,
337
338 // Thumb format
339 ThumbFrm = 25 << FormShift,
340
341 // Miscelleaneous format
342 MiscFrm = 26 << FormShift,
343
344 // NEON formats
345 NGetLnFrm = 27 << FormShift,
346 NSetLnFrm = 28 << FormShift,
347 NDupFrm = 29 << FormShift,
348 NLdStFrm = 30 << FormShift,
349 N1RegModImmFrm= 31 << FormShift,
350 N2RegFrm = 32 << FormShift,
351 NVCVTFrm = 33 << FormShift,
352 NVDupLnFrm = 34 << FormShift,
353 N2RegVShLFrm = 35 << FormShift,
354 N2RegVShRFrm = 36 << FormShift,
355 N3RegFrm = 37 << FormShift,
356 N3RegVShFrm = 38 << FormShift,
357 NVExtFrm = 39 << FormShift,
358 NVMulSLFrm = 40 << FormShift,
359 NVTBLFrm = 41 << FormShift,
360
361 //===------------------------------------------------------------------===//
362 // Misc flags.
363
364 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
365 // it doesn't have a Rn operand.
366 UnaryDP = 1 << 13,
367
368 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
369 // a 16-bit Thumb instruction if certain conditions are met.
370 Xform16Bit = 1 << 14,
371
372 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
373 // instruction. Used by the parser to determine whether to require the 'S'
374 // suffix on the mnemonic (when not in an IT block) or preclude it (when
375 // in an IT block).
376 ThumbArithFlagSetting = 1 << 18,
377
378 //===------------------------------------------------------------------===//
379 // Code domain.
380 DomainShift = 15,
381 DomainMask = 7 << DomainShift,
382 DomainGeneral = 0 << DomainShift,
383 DomainVFP = 1 << DomainShift,
384 DomainNEON = 2 << DomainShift,
385 DomainNEONA8 = 4 << DomainShift,
386
387 //===------------------------------------------------------------------===//
388 // Field shifts - such shifts are used to set field while generating
389 // machine instructions.
390 //
391 // FIXME: This list will need adjusting/fixing as the MC code emitter
392 // takes shape and the ARMCodeEmitter.cpp bits go away.
393 ShiftTypeShift = 4,
394
395 M_BitShift = 5,
396 ShiftImmShift = 5,
397 ShiftShift = 7,
398 N_BitShift = 7,
399 ImmHiShift = 8,
400 SoRotImmShift = 8,
401 RegRsShift = 8,
402 ExtRotImmShift = 10,
403 RegRdLoShift = 12,
404 RegRdShift = 12,
405 RegRdHiShift = 16,
406 RegRnShift = 16,
407 S_BitShift = 20,
408 W_BitShift = 21,
409 AM3_I_BitShift = 22,
410 D_BitShift = 22,
411 U_BitShift = 23,
412 P_BitShift = 24,
413 I_BitShift = 25,
414 CondShift = 28
415 };
416
417 } // end namespace ARMII
418
419 } // end namespace llvm;
420
421 #endif
422