1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Mips16InstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24
25 using namespace llvm;
26
Mips16InstrInfo(MipsTargetMachine & tm)27 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
28 : MipsInstrInfo(tm, /* FIXME: set mips16 unconditional br */ 0),
29 RI(*tm.getSubtargetImpl()) {}
30
getRegisterInfo() const31 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
32 return RI;
33 }
34
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned Mips16InstrInfo::
isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex) const41 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
42 {
43 return 0;
44 }
45
46 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// store to a stack slot, return the virtual or physical register number of
48 /// the source reg along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than storing to the stack slot.
51 unsigned Mips16InstrInfo::
isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex) const52 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
53 {
54 return 0;
55 }
56
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const57 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator I, DebugLoc DL,
59 unsigned DestReg, unsigned SrcReg,
60 bool KillSrc) const {
61 unsigned Opc = 0, ZeroReg = 0;
62
63 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
64 if (Mips::CPURegsRegClass.contains(SrcReg))
65 Opc = Mips::Mov32R16;
66 }
67
68 assert(Opc && "Cannot copy registers");
69
70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
71
72 if (DestReg)
73 MIB.addReg(DestReg, RegState::Define);
74
75 if (ZeroReg)
76 MIB.addReg(ZeroReg);
77
78 if (SrcReg)
79 MIB.addReg(SrcReg, getKillRegState(KillSrc));
80 }
81
82 void Mips16InstrInfo::
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84 unsigned SrcReg, bool isKill, int FI,
85 const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const {
87 assert(false && "Implement this function.");
88 }
89
90 void Mips16InstrInfo::
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const91 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
92 unsigned DestReg, int FI,
93 const TargetRegisterClass *RC,
94 const TargetRegisterInfo *TRI) const {
95 assert(false && "Implement this function.");
96 }
97
expandPostRAPseudo(MachineBasicBlock::iterator MI) const98 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
99 MachineBasicBlock &MBB = *MI->getParent();
100
101 switch(MI->getDesc().getOpcode()) {
102 default:
103 return false;
104 case Mips::RetRA16:
105 ExpandRetRA16(MBB, MI, Mips::JrRa16);
106 break;
107 }
108
109 MBB.erase(MI);
110 return true;
111 }
112
113 /// GetOppositeBranchOpc - Return the inverse of the specified
114 /// opcode, e.g. turning BEQ to BNE.
GetOppositeBranchOpc(unsigned Opc) const115 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
116 assert(false && "Implement this function.");
117 return 0;
118 }
119
GetAnalyzableBrOpc(unsigned Opc) const120 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
121 return 0;
122 }
123
ExpandRetRA16(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned Opc) const124 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I,
126 unsigned Opc) const {
127 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
128 }
129
createMips16InstrInfo(MipsTargetMachine & TM)130 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
131 return new Mips16InstrInfo(TM);
132 }
133