1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
16
17 #include "X86.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
24
25 namespace llvm {
26 class X86RegisterInfo;
27 class X86TargetMachine;
28
29 namespace X86 {
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
32 enum CondCode {
33 COND_A = 0,
34 COND_AE = 1,
35 COND_B = 2,
36 COND_BE = 3,
37 COND_E = 4,
38 COND_G = 5,
39 COND_GE = 6,
40 COND_L = 7,
41 COND_LE = 8,
42 COND_NE = 9,
43 COND_NO = 10,
44 COND_NP = 11,
45 COND_NS = 12,
46 COND_O = 13,
47 COND_P = 14,
48 COND_S = 15,
49
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
55 COND_NE_OR_P,
56 COND_NP_OR_E,
57
58 COND_INVALID
59 };
60
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
63
64 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
65 /// e.g. turning COND_E to COND_NE.
66 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 } // end namespace X86;
68
69
70 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
71 /// a reference to a stub for a global, not the global itself.
isGlobalStubReference(unsigned char TargetFlag)72 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
73 switch (TargetFlag) {
74 case X86II::MO_DLLIMPORT: // dllimport stub.
75 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
76 case X86II::MO_GOT: // normal GOT reference.
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
78 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
79 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
80 return true;
81 default:
82 return false;
83 }
84 }
85
86 /// isGlobalRelativeToPICBase - Return true if the specified global value
87 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
88 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
isGlobalRelativeToPICBase(unsigned char TargetFlag)89 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
90 switch (TargetFlag) {
91 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
92 case X86II::MO_GOT: // isPICStyleGOT: other global.
93 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
94 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
95 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
96 case X86II::MO_TLVP: // ??? Pretty sure..
97 return true;
98 default:
99 return false;
100 }
101 }
102
isScale(const MachineOperand & MO)103 inline static bool isScale(const MachineOperand &MO) {
104 return MO.isImm() &&
105 (MO.getImm() == 1 || MO.getImm() == 2 ||
106 MO.getImm() == 4 || MO.getImm() == 8);
107 }
108
isLeaMem(const MachineInstr * MI,unsigned Op)109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI());
118 }
119
isMem(const MachineInstr * MI,unsigned Op)120 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
121 if (MI->getOperand(Op).isFI()) return true;
122 return Op+5 <= MI->getNumOperands() &&
123 MI->getOperand(Op+4).isReg() &&
124 isLeaMem(MI, Op);
125 }
126
127 class X86InstrInfo : public X86GenInstrInfo {
128 X86TargetMachine &TM;
129 const X86RegisterInfo RI;
130
131 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
132 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
133 ///
134 typedef DenseMap<unsigned,
135 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
136 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
137 RegOp2MemOpTableType RegOp2MemOpTable0;
138 RegOp2MemOpTableType RegOp2MemOpTable1;
139 RegOp2MemOpTableType RegOp2MemOpTable2;
140 RegOp2MemOpTableType RegOp2MemOpTable3;
141
142 /// MemOp2RegOpTable - Load / store unfolding opcode map.
143 ///
144 typedef DenseMap<unsigned,
145 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
146 MemOp2RegOpTableType MemOp2RegOpTable;
147
148 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
149 MemOp2RegOpTableType &M2RTable,
150 unsigned RegOp, unsigned MemOp, unsigned Flags);
151
152 public:
153 explicit X86InstrInfo(X86TargetMachine &tm);
154
155 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
156 /// such, whenever a client has an instance of instruction info, it should
157 /// always be able to get register info as well (through this method).
158 ///
getRegisterInfo()159 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
160
161 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
162 /// extension instruction. That is, it's like a copy where it's legal for the
163 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
164 /// true, then it's expected the pre-extension value is available as a subreg
165 /// of the result register. This also returns the sub-register index in
166 /// SubIdx.
167 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
168 unsigned &SrcReg, unsigned &DstReg,
169 unsigned &SubIdx) const;
170
171 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
172 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
173 /// stack locations as well. This uses a heuristic so it isn't
174 /// reliable for correctness.
175 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
176 int &FrameIndex) const;
177
178 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
179 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
180 /// stack locations as well. This uses a heuristic so it isn't
181 /// reliable for correctness.
182 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
183 int &FrameIndex) const;
184
185 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
186 AliasAnalysis *AA) const;
187 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
188 unsigned DestReg, unsigned SubIdx,
189 const MachineInstr *Orig,
190 const TargetRegisterInfo &TRI) const;
191
192 /// convertToThreeAddress - This method must be implemented by targets that
193 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
194 /// may be able to convert a two-address instruction into a true
195 /// three-address instruction on demand. This allows the X86 target (for
196 /// example) to convert ADD and SHL instructions into LEA instructions if they
197 /// would require register copies due to two-addressness.
198 ///
199 /// This method returns a null pointer if the transformation cannot be
200 /// performed, otherwise it returns the new instruction.
201 ///
202 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
203 MachineBasicBlock::iterator &MBBI,
204 LiveVariables *LV) const;
205
206 /// commuteInstruction - We have a few instructions that must be hacked on to
207 /// commute them.
208 ///
209 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
210
211 // Branch analysis.
212 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
213 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
214 MachineBasicBlock *&FBB,
215 SmallVectorImpl<MachineOperand> &Cond,
216 bool AllowModify) const;
217 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
218 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
219 MachineBasicBlock *FBB,
220 const SmallVectorImpl<MachineOperand> &Cond,
221 DebugLoc DL) const;
222 virtual bool canInsertSelect(const MachineBasicBlock&,
223 const SmallVectorImpl<MachineOperand> &Cond,
224 unsigned, unsigned, int&, int&, int&) const;
225 virtual void insertSelect(MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator MI, DebugLoc DL,
227 unsigned DstReg,
228 const SmallVectorImpl<MachineOperand> &Cond,
229 unsigned TrueReg, unsigned FalseReg) const;
230 virtual void copyPhysReg(MachineBasicBlock &MBB,
231 MachineBasicBlock::iterator MI, DebugLoc DL,
232 unsigned DestReg, unsigned SrcReg,
233 bool KillSrc) const;
234 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MI,
236 unsigned SrcReg, bool isKill, int FrameIndex,
237 const TargetRegisterClass *RC,
238 const TargetRegisterInfo *TRI) const;
239
240 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
241 SmallVectorImpl<MachineOperand> &Addr,
242 const TargetRegisterClass *RC,
243 MachineInstr::mmo_iterator MMOBegin,
244 MachineInstr::mmo_iterator MMOEnd,
245 SmallVectorImpl<MachineInstr*> &NewMIs) const;
246
247 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
248 MachineBasicBlock::iterator MI,
249 unsigned DestReg, int FrameIndex,
250 const TargetRegisterClass *RC,
251 const TargetRegisterInfo *TRI) const;
252
253 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
254 SmallVectorImpl<MachineOperand> &Addr,
255 const TargetRegisterClass *RC,
256 MachineInstr::mmo_iterator MMOBegin,
257 MachineInstr::mmo_iterator MMOEnd,
258 SmallVectorImpl<MachineInstr*> &NewMIs) const;
259
260 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
261
262 virtual
263 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
264 int FrameIx, uint64_t Offset,
265 const MDNode *MDPtr,
266 DebugLoc DL) const;
267
268 /// foldMemoryOperand - If this target supports it, fold a load or store of
269 /// the specified stack slot into the specified machine instruction for the
270 /// specified operand(s). If this is possible, the target should perform the
271 /// folding and return true, otherwise it should return false. If it folds
272 /// the instruction, it is likely that the MachineInstruction the iterator
273 /// references has been changed.
274 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
275 MachineInstr* MI,
276 const SmallVectorImpl<unsigned> &Ops,
277 int FrameIndex) const;
278
279 /// foldMemoryOperand - Same as the previous version except it allows folding
280 /// of any load and store from / to any address, not just from a specific
281 /// stack slot.
282 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
283 MachineInstr* MI,
284 const SmallVectorImpl<unsigned> &Ops,
285 MachineInstr* LoadMI) const;
286
287 /// canFoldMemoryOperand - Returns true if the specified load / store is
288 /// folding is possible.
289 virtual bool canFoldMemoryOperand(const MachineInstr*,
290 const SmallVectorImpl<unsigned> &) const;
291
292 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
293 /// a store or a load and a store into two or more instruction. If this is
294 /// possible, returns true as well as the new instructions by reference.
295 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
296 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
297 SmallVectorImpl<MachineInstr*> &NewMIs) const;
298
299 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
300 SmallVectorImpl<SDNode*> &NewNodes) const;
301
302 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
303 /// instruction after load / store are unfolded from an instruction of the
304 /// specified opcode. It returns zero if the specified unfolding is not
305 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
306 /// index of the operand which will hold the register holding the loaded
307 /// value.
308 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
309 bool UnfoldLoad, bool UnfoldStore,
310 unsigned *LoadRegIndex = 0) const;
311
312 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
313 /// to determine if two loads are loading from the same base address. It
314 /// should only return true if the base pointers are the same and the
315 /// only differences between the two addresses are the offset. It also returns
316 /// the offsets by reference.
317 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
318 int64_t &Offset1, int64_t &Offset2) const;
319
320 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
321 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
322 /// be scheduled togther. On some targets if two loads are loading from
323 /// addresses in the same cache line, it's better if they are scheduled
324 /// together. This function takes two integers that represent the load offsets
325 /// from the common base address. It returns true if it decides it's desirable
326 /// to schedule the two loads together. "NumLoads" is the number of loads that
327 /// have already been scheduled after Load1.
328 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
329 int64_t Offset1, int64_t Offset2,
330 unsigned NumLoads) const;
331
332 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
333
334 virtual
335 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
336
337 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
338 /// instruction that defines the specified register class.
339 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
340
isX86_64ExtendedReg(const MachineOperand & MO)341 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
342 if (!MO.isReg()) return false;
343 return X86II::isX86_64ExtendedReg(MO.getReg());
344 }
345
346 /// getGlobalBaseReg - Return a virtual register initialized with the
347 /// the global base register value. Output instructions required to
348 /// initialize the register in the function entry block, if necessary.
349 ///
350 unsigned getGlobalBaseReg(MachineFunction *MF) const;
351
352 std::pair<uint16_t, uint16_t>
353 getExecutionDomain(const MachineInstr *MI) const;
354
355 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
356
357 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
358 const TargetRegisterInfo *TRI) const;
359 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
360 const TargetRegisterInfo *TRI) const;
361
362 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
363 MachineInstr* MI,
364 unsigned OpNum,
365 const SmallVectorImpl<MachineOperand> &MOs,
366 unsigned Size, unsigned Alignment) const;
367
368 bool isHighLatencyDef(int opc) const;
369
370 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
371 const MachineRegisterInfo *MRI,
372 const MachineInstr *DefMI, unsigned DefIdx,
373 const MachineInstr *UseMI, unsigned UseIdx) const;
374
375 /// analyzeCompare - For a comparison instruction, return the source registers
376 /// in SrcReg and SrcReg2 if having two register operands, and the value it
377 /// compares against in CmpValue. Return true if the comparison instruction
378 /// can be analyzed.
379 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
380 unsigned &SrcReg2,
381 int &CmpMask, int &CmpValue) const;
382
383 /// optimizeCompareInstr - Check if there exists an earlier instruction that
384 /// operates on the same source operands and sets flags in the same way as
385 /// Compare; remove Compare if possible.
386 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
387 unsigned SrcReg2, int CmpMask, int CmpValue,
388 const MachineRegisterInfo *MRI) const;
389
390 /// optimizeLoadInstr - Try to remove the load by folding it to a register
391 /// operand at the use. We fold the load instructions if and only if the
392 /// def and use are in the same BB. We only look at one load and see
393 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
394 /// defined by the load we are trying to fold. DefMI returns the machine
395 /// instruction that defines FoldAsLoadDefReg, and the function returns
396 /// the machine instruction generated due to folding.
397 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
398 const MachineRegisterInfo *MRI,
399 unsigned &FoldAsLoadDefReg,
400 MachineInstr *&DefMI) const;
401
402 private:
403 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
404 MachineFunction::iterator &MFI,
405 MachineBasicBlock::iterator &MBBI,
406 LiveVariables *LV) const;
407
408 /// isFrameOperand - Return true and the FrameIndex if the specified
409 /// operand and follow operands form a reference to the stack frame.
410 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
411 int &FrameIndex) const;
412 };
413
414 } // End llvm namespace
415
416 #endif
417