| /dalvik/vm/compiler/codegen/x86/libenc/ |
| D | enc_prvt.h | 140 #define AX {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_AX}
152 #define DX {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_DX}
169 #define r16 {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_Null}
176 #define r_m16 {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Any, RegName_Nul…
180 #define r_m16s {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Signed, RegName…
184 #define r_m16u {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Zero, RegName_N…
191 #define m16 {OpndKind_Mem, OpndSize_16, OpndExt_Any, RegName_Null}
199 #define imm16 {OpndKind_Imm, OpndSize_16, OpndExt_Any, RegName_Null}
203 #define imm16s {OpndKind_Imm, OpndSize_16, OpndExt_Signed, RegName_Null}
207 #define imm16u {OpndKind_Imm, OpndSize_16, OpndExt_Zero, RegName_Null}
[all …]
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| D | enc_defs.h | 207 RegName_AX=REGNAME(OpndKind_GPReg,OpndSize_16,0),
208 RegName_CX=REGNAME(OpndKind_GPReg,OpndSize_16,1),
209 RegName_DX=REGNAME(OpndKind_GPReg,OpndSize_16,2),
210 RegName_BX=REGNAME(OpndKind_GPReg,OpndSize_16,3),
211 RegName_SP=REGNAME(OpndKind_GPReg,OpndSize_16,4),
212 RegName_BP=REGNAME(OpndKind_GPReg,OpndSize_16,5),
213 RegName_SI=REGNAME(OpndKind_GPReg,OpndSize_16,6),
214 RegName_DI=REGNAME(OpndKind_GPReg,OpndSize_16,7),
217 RegName_R8S = REGNAME(OpndKind_GPReg,OpndSize_16,8),
218 RegName_R9S = REGNAME(OpndKind_GPReg,OpndSize_16,9),
[all …]
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| D | encoder.cpp | 120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
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| D | enc_defs_ext.h | 42 OpndSize_16 = 0x02, enumerator
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| D | dec_base.cpp | 257 opnd_size = OpndSize_16; in decode_aux()
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| D | enc_base.h | 358 m_kind(OpndKind_Imm), m_size(OpndSize_16), m_ext(ext), m_imm64(ival) in m_kind()
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| D | enc_base.cpp | 881 { "Sz16", OpndSize_16 },
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| D | encoder.inl | 739 EncoderBase::Operands args(EncoderBase::Operand(OpndSize_16, pop, OpndExt_Zero));
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| D | enc_tabl.cpp | 1883 else if (sz==OpndSize_16) {imm_encode = iw; coff_encode=cw;} in buildMnemonicDesc()
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| /dalvik/vm/compiler/codegen/x86/ |
| D | LowerJump.cpp | 91 if(immSize == OpndSize_16) { //-2^16 to 2^16-1 in updateJumpInst()
420 if(target-MIN_JCC_SIZE < 32768 && target-MAX_JCC_SIZE >= -32768) return OpndSize_16; in estOpndSizeFromImm()
431 if(size == OpndSize_16) return 4; in getJmpCallInstSize()
436 if(size == OpndSize_16) return 5; in getJmpCallInstSize()
445 if(size == OpndSize_16) return 4; in getJmpCallInstSize()
481 *immSize = OpndSize_16; in getRelativeOffset()
495 *immSize = OpndSize_16; in getRelativeOffset()
508 *immSize = OpndSize_16; in getRelativeOffset()
890 *size = OpndSize_16; in getRelativeNCG()
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| D | LowerGetPut.cpp | 73 …movez_mem_disp_scale_to_reg(OpndSize_16, 1, false, offArrayObject_contents, 2, false, 2, 4, false); in aget_common_nohelper()
76 …moves_mem_disp_scale_to_reg(OpndSize_16, 1, false, offArrayObject_contents, 2, false, 2, 4, false); in aget_common_nohelper()
228 … move_reg_to_mem_disp_scale(OpndSize_16, 4, false, 1, false, offArrayObject_contents, 2, false, 2); in aput_common_nohelper()
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| D | LowerInvoke.cpp | 765 …movez_mem_to_reg(OpndSize_16, offMethod_registersSize, PhysicalReg_ECX, true, P_SCRATCH_1, true); … in common_invokeArgsDone()
773 …movez_mem_to_reg(OpndSize_16, offMethod_outsSize, PhysicalReg_ECX, true, P_SCRATCH_2, true); //out… in common_invokeArgsDone()
1066 movez_mem_disp_scale_to_reg(OpndSize_16, 5, false, 0, 1, false, 2, in op_execute_inline()
1078 movez_mem_to_reg(OpndSize_16, 0, 5, false, 6, false); in op_execute_inline()
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| D | LowerAlu.cpp | 228 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true); in common_fp_to_int()
230 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true); in common_fp_to_int()
309 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true); in common_fp_to_long()
311 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true); in common_fp_to_long()
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| D | LowerHelper.cpp | 817 dump_mem(m, ATOM_NORMAL, OpndSize_16, disp, base_reg, isBasePhysical); in load_fpu_cw()
825 dump_mem(m, ATOM_NORMAL, OpndSize_16, disp, base_reg, isBasePhysical); in store_fpu_cw()
1138 …dump_reg_reg(m, ATOM_NORMAL, OpndSize_16, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp); in compare_reg_reg_16()
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