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Searched refs:CP0C0_K0 (Results 1 – 2 of 2) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c25 ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
314 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
333 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
Dcpu.h334 #define CP0C0_K0 0 macro