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Searched refs:CP0_SRSCtl (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c79 int32_t CP0_SRSCtl; member
288 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
Dmachine.c117 qemu_put_sbe32s(f, &env->CP0_SRSCtl); in cpu_save()
268 qemu_get_sbe32s(f, &env->CP0_SRSCtl); in cpu_load()
Dcpu.h293 int32_t CP0_SRSCtl; member
Dtranslate.c557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_load_srsgpr()
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_store_srsgpr()
3173 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); in gen_mfc0()
4341 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); in gen_dmfc0()
8631 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; in cpu_reset()
Dop_helper.c1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); in helper_mtc0_srsctl()