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Searched refs:IMPLICIT_DEF (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/include/llvm/Target/
DTargetOpcodes.h52 IMPLICIT_DEF = 8, enumerator
DTargetInstrInfo.h70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
/external/llvm/test/CodeGen/X86/
Dinsertelement-copytoregs.ll1 ; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
Dfp-stack-O0-crash.ll33 ; This produces a FP0 = IMPLICIT_DEF instruction.
D2008-01-16-InvalidDAGCombineXform.ll1 ; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
/external/llvm/test/CodeGen/PowerPC/
D2006-10-13-Miscompile.ll1 ; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
/external/llvm/test/CodeGen/Generic/
Dundef-phi.ll4 ; inserts an IMPLICIT_DEF instruction in the predecessor so all paths to the use
/external/llvm/lib/CodeGen/
DMachineSSAUpdater.cpp149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
297 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
DProcessImplicitDefs.cpp92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in processImplicitDef()
DPHIElimination.cpp226 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerAtomicPHINode()
324 TII->get(TargetOpcode::IMPLICIT_DEF), IncomingReg); in LowerAtomicPHINode()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp268 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
308 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
555 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in initNumRegDefsLeft()
DInstrEmitter.cpp210 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
718 if (Opc == TargetOpcode::IMPLICIT_DEF) in EmitMachineNode()
DScheduleDAGSDNodes.cpp82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) in newSUnit()
538 if (POpc == TargetOpcode::IMPLICIT_DEF) { in InitNodeNumDefs()
DScheduleDAGRRList.cpp2089 Opc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
2112 if (POpc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h611 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
660 case TargetOpcode::IMPLICIT_DEF:
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp210 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) { in EmitInstruction()
DHexagonMachineScheduler.cpp239 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
284 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
/external/llvm/lib/Target/X86/
DX86InstrSSE.td273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
1492 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1494 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1496 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1498 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
[all …]
DX86CodeEmitter.cpp1184 case TargetOpcode::IMPLICIT_DEF: in emitInstruction()
/external/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp124 case TargetOpcode::IMPLICIT_DEF: in emitBasicBlock()
DPPCInstr64Bit.td809 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
812 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp301 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5079 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5081 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5083 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5086 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5088 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5090 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5093 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5094 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5097 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5098 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
[all …]
DARMISelDAGToDAG.cpp1678 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); in SelectVLD()
1789 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) in SelectVST()
1837 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVST()
1955 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVLDSTLane()
2092 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVTBL()
/external/llvm/lib/Target/NVPTX/
DVectorElementize.cpp154 (mi->getOpcode() == NVPTX::IMPLICIT_DEF) || mi->isCopy()) { in isVectorInstr()
731 if (opcode == NVPTX::IMPLICIT_DEF) in getScalarVersion()

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