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Searched refs:INSERT_SUBREG (Results 1 – 16 of 16) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetOpcodes.h49 INSERT_SUBREG = 7, enumerator
DTarget.td703 def INSERT_SUBREG : Instruction {
/external/llvm/test/CodeGen/X86/
Dcrash-nosse.ll5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp226 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h616 return getOpcode() == TargetOpcode::INSERT_SUBREG;
656 case TargetOpcode::INSERT_SUBREG:
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp265 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
305 case TargetOpcode::INSERT_SUBREG: in reserveResources()
DScheduleDAGRRList.cpp1867 Opc == TargetOpcode::INSERT_SUBREG) in getNodePriority()
2086 Opc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2115 POpc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2558 Opc == TargetOpcode::INSERT_SUBREG) in canEnableCoalescing()
2929 SuccOpc == TargetOpcode::INSERT_SUBREG || in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp515 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
700 Opc == TargetOpcode::INSERT_SUBREG || in EmitMachineNode()
DSelectionDAG.cpp5301 SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL, in getTargetInsertSubreg()
/external/llvm/test/CodeGen/Thumb2/
Dcrash.ll27 ; The first INSERT_SUBREG needs an <undef> use operand for that to work.
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp236 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
281 case TargetOpcode::INSERT_SUBREG: in reserveResources()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5062 (v4i32 (INSERT_SUBREG QPR:$src1,
5067 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5070 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5074 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5076 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5079 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5081 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5083 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5093 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5097 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td809 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
812 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
/external/llvm/lib/Target/X86/
DX86InstrSSE.td273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
457 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
7750 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7754 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7761 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
[all …]
DREADME.txt77 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
DX86InstrCompiler.td1140 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;