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Searched refs:InstrStage (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td63 InstrItinData<IntSimple , [InstrStage<4,
65 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
67 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
68 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
69 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
70 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
71 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
74 InstrItinData<IntGeneral , [InstrStage<4,
76 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
78 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
[all …]
DPPCSchedule440.td111 InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>,
112 InstrStage<1, [PDCD1, PDCD2]>,
113 InstrStage<1, [DISS1, DISS2]>,
114 InstrStage<1, [IRACC, LRACC]>,
115 InstrStage<1, [IEXE1, JEXE1]>,
116 InstrStage<1, [IEXE2, JEXE2]>,
117 InstrStage<1, [IWB, JWB]>],
120 InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
121 InstrStage<1, [PDCD1, PDCD2]>,
122 InstrStage<1, [DISS1, DISS2]>,
[all …]
DPPCScheduleG5.td16 InstrItinData<IntSimple , [InstrStage<2, [IU1, IU2]>]>,
17 InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
18 InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>,
19 InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>,
20 InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>,
21 InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>,
22 InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>,
23 InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
24 InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
25 InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
[all …]
DPPCScheduleG4Plus.td19 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
20 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
21 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
22 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
23 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
24 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
25 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
26 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
27 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
28 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
[all …]
DPPCScheduleG4.td16 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
17 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
18 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
19 InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
20 InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>,
21 InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>,
22 InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
23 InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
24 InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
25 InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
[all …]
DPPCScheduleG3.td17 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
18 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
19 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
20 InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
21 InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
22 InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
23 InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
24 InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
25 InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
26 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
[all …]
DPPCScheduleE5500.td47 InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>,
48 InstrStage<1, [SFX0, SFX1]>],
51 InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
52 InstrStage<1, [SFX0, SFX1]>],
55 InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>,
56 InstrStage<1, [SFX0, SFX1]>],
59 InstrItinData<IntDivD , [InstrStage<1, [DIS0, DIS1], 0>,
60 InstrStage<1, [CFX_0], 0>,
61 InstrStage<26, [CFX_DivBypass]>],
64 InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>,
[all …]
DPPCScheduleE500mc.td42 InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>,
43 InstrStage<1, [SFX0, SFX1]>],
46 InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
47 InstrStage<1, [SFX0, SFX1]>],
50 InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>,
51 InstrStage<1, [SFX0, SFX1]>],
54 InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>,
55 InstrStage<1, [CFX_0], 0>,
56 InstrStage<14, [CFX_DivBypass]>],
59 InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>,
[all …]
/external/llvm/lib/Target/ARM/
DARMScheduleA9.td46 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
48 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
52 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
53 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
54 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
55 InstrStage<1, [A9_ALU0, A9_ALU1]>,
[all …]
DARMScheduleA8.td31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
[all …]
DARMScheduleV6.td25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
[all …]
/external/llvm/lib/Target/X86/
DX86ScheduleAtom.td29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
36 InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
37 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
38 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
39 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
40 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
[all …]
/external/llvm/lib/Target/Mips/
DMipsSchedule.td44 InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
45 InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
46 InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
47 InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,
48 InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>,
49 InstrItinData<IIHiLo , [InstrStage<1, [IMULDIV]>]>,
50 InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
51 InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
52 InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
53 InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
[all …]
/external/llvm/lib/Target/MBlaze/
DMBlazeSchedule5.td22 [ InstrStage<1,[IF]> // one cycle in fetch stage
23 , InstrStage<1,[ID]> // one cycle in decode stage
24 , InstrStage<1,[EX]> // one cycle in execute stage
25 , InstrStage<1,[MA]> // one cycle in memory access stage
26 , InstrStage<1,[WB]>], // one cycle in write back stage
37 [ InstrStage<1,[IF]> // one cycle in fetch stage
38 , InstrStage<1,[ID]> // one cycle in decode stage
39 , InstrStage<1,[EX]> // one cycle in execute stage
40 , InstrStage<1,[MA]> // one cycle in memory access stage
41 , InstrStage<1,[WB]>], // one cycle in write back stage
[all …]
DMBlazeSchedule3.td22 [ InstrStage<1,[IF]> // one cycle in fetch stage
23 , InstrStage<1,[ID]> // one cycle in decode stage
24 , InstrStage<1,[EX]>], // one cycle in execute stage
36 [ InstrStage<1,[IF]> // one cycle in fetch stage
37 , InstrStage<1,[ID]> // one cycle in decode stage
38 , InstrStage<3,[EX]>], // three cycles in execute stage
49 [ InstrStage<1,[IF]> // one cycle in fetch stage
50 , InstrStage<1,[ID]> // one cycle in decode stage
51 , InstrStage<34,[EX]>], // 34 cycles in execute stage
63 [ InstrStage<1,[IF]> // one cycle in fetch stage
[all …]
/external/llvm/lib/Target/CellSPU/
DSPUSchedule.td41 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
42 InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>,
43 InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>,
44 InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>,
45 InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>,
46 InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>,
47 InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>,
48 InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>,
49 InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>,
50 InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>,
[all …]
DSPUNopFiller.cpp140 const InstrStage *stage = IID->beginStage(sc); in getOpPlacement()
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td40 InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
41 InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,
42 InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,
43 InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,
44 InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,
45 InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,
46 InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,
47 InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,
48 InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>,
49 InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>,
[all …]
DHexagonSchedule.td32 InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
33 InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
34 InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
35 InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
36 InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
37 InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
38 InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
39 InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
40 InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
41 InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
[all …]
/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp51 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
52 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
134 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
153 case InstrStage::Required: in getHazardType()
157 case InstrStage::Reserved: in getHazardType()
194 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
205 case InstrStage::Required: in EmitInstruction()
209 case InstrStage::Reserved: in EmitInstruction()
222 if (IS->getReservationKind() == InstrStage::Required) in EmitInstruction()
DDFAPacketizer.cpp68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in canReserveResources()
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in reserveResources()
/external/llvm/include/llvm/MC/
DMCInstrItineraries.h59 struct InstrStage { struct
114 const InstrStage *Stages; ///< Array of stages selected
125 InstrItineraryData(const MCSchedModel *SM, const InstrStage *S, in InstrItineraryData()
144 const InstrStage *beginStage(unsigned ItinClassIndx) const { in beginStage()
151 const InstrStage *endStage(unsigned ItinClassIndx) const { in endStage()
174 for (const InstrStage *IS = beginStage(ItinClassIndx), in getStageLatency()
DMCSubtargetInfo.h34 const InstrStage *Stages; // Instruction itinerary stages
46 const InstrStage *IS,
/external/llvm/include/llvm/Target/
DTargetItinerary.td53 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
54 // InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit
57 class InstrStage<int cycles, list<FuncUnit> units,
99 // InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
100 // InstrStage<1, [A9_AGU]>],
102 // InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>],
110 class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
115 list<InstrStage> Stages = stages;
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp27 const InstrStage *IS, in InitMCSubtargetInfo()

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