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Searched refs:MVN (Results 1 – 21 of 21) sorted by relevance

/external/tremolo/Tremolo/
DbitwiseARM.s128 @MVN r0,#0 ; return -1
366 MVN r1,#0 @ r1 = -1 = bitsLeftInSegment
368 @MVN r0,#0 ; return -1
Ddpen.s54 MVN r0,#0 @ return -1
393 MVN r0,#0
449 MVN r0, #0 @ return -1
DmdctLARM.s55 MVN r4, #0x8000
114 MVN r4, #0x8000
190 MVN r4, #0x8000
230 MVN r4, #0x8000
DmdctARM.s55 MVN r4, #0x8000
114 MVN r4, #0x8000
190 MVN r4, #0x8000
229 MVN r4, #0x8000
/external/webkit/Source/JavaScriptCore/assembler/
DARMAssembler.h140 MVN = (0xf << 21), enumerator
427 emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2);
432 emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
/external/v8/src/arm/
Dconstants-arm.h206 MVN = 15 << 21 // Move Not. enumerator
Ddisasm-arm.cc907 case MVN: { in DecodeType01()
Dassembler-arm.cc1185 addrmod1(cond | MVN | s, r0, dst, src); in mvn()
Dsimulator-arm.cc2457 case MVN: { in DecodeType01()
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt296 # MVN
Dbasic-arm-instructions.txt859 # MVN (immediate)
877 # MVN (register)
901 # MVN (shifted register)
Dthumb2.txt1087 # MVN(immediate)
1107 # MVN(register)
/external/llvm/lib/Target/ARM/
DARMScheduleV6.td82 // MVN instructions
DARMScheduleA8.td89 // MVN instructions
DARMScheduleA9.td68 // MVN instructions
DARMInstrThumb2.td4104 // Alias for MVN with(out) the ".w" optional width specifier.
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s406 @ MVN
Dbasic-arm-instructions.s1168 @ MVN (immediate)
1186 @ MVN (register)
1210 @ MVN (shifted register)
Dbasic-thumb2-instructions.s1416 @ MVN(immediate)
1436 @ MVN(register)
/external/valgrind/main/none/tests/arm/
Dv6intARM.stdout.exp16 MVN
755 MVN
Dv6intThumb.stdout.exp14894 MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto
16524 (T2) MVN{S}.W Rd, #constT
16785 MVN
30877 MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto
32507 (T2) MVN{S}.W Rd, #constT
32669 MVN