Searched refs:MinLatency (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/include/llvm/MC/ |
| D | MCSchedule.h | 63 int MinLatency; variable
99 MinLatency(DefaultMinLatency), in MCSchedModel()
108 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), in MCSchedModel()
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| D | MCInstrItineraries.h | 170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency; in getStageLatency()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 89 unsigned MinLatency; variable
101 : Dep(S, kind), Contents(), Latency(latency), MinLatency(latency) { in Dep()
141 && Latency == Other.Latency && MinLatency == Other.MinLatency;
165 return MinLatency; in getMinLatency()
170 MinLatency = Lat; in setMinLatency()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 487 unsigned MinLatency = I->getMinLatency(); in releaseTopNode() local
489 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency); in releaseTopNode()
491 if (SU->TopReadyCycle < PredReadyCycle + MinLatency) in releaseTopNode()
492 SU->TopReadyCycle = PredReadyCycle + MinLatency; in releaseTopNode()
506 unsigned MinLatency = I->getMinLatency(); in releaseBottomNode() local
508 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency); in releaseBottomNode()
510 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency) in releaseBottomNode()
511 SU->BotReadyCycle = SuccReadyCycle + MinLatency; in releaseBottomNode()
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 910 unsigned MinLatency = I->getMinLatency(); in releaseTopNode() local
912 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency); in releaseTopNode()
914 if (SU->TopReadyCycle < PredReadyCycle + MinLatency) in releaseTopNode()
915 SU->TopReadyCycle = PredReadyCycle + MinLatency; in releaseTopNode()
929 unsigned MinLatency = I->getMinLatency(); in releaseBottomNode() local
931 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency); in releaseBottomNode()
933 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency) in releaseBottomNode()
934 SU->BotReadyCycle = SuccReadyCycle + MinLatency; in releaseBottomNode()
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| D | ScheduleDAGInstrs.cpp | 281 unsigned MinLatency = in addPhysRegDataDeps() local
285 dep.setMinLatency(MinLatency); in addPhysRegDataDeps()
483 unsigned MinLatency = in addVRegUseDeps() local
486 dep.setMinLatency(MinLatency); in addVRegUseDeps()
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| D | TargetInstrInfoImpl.cpp | 623 if (ItinData->SchedModel->MinLatency >= 0) in computeDefOperandLatency()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 26 int MinLatency = -1; // Determines which instrucions are allowed in a group.
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleE500mc.td | 259 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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| D | PPCScheduleE5500.td | 303 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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| /external/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 464 // MinLatency=0 indicates that RAW dependencies can be decoded in the
476 let MinLatency = 0;
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| D | X86ScheduleAtom.td | 524 let MinLatency = 1; // InstrStage cycles overrides MinLatency.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA8.td | 1068 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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| D | ARMScheduleA9.td | 1885 let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
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