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Searched refs:OP_SH_RS (Results 1 – 2 of 2) sorted by relevance

/external/webkit/Source/JavaScriptCore/assembler/
DMIPSAssembler.h161 OP_SH_RS = 21, enumerator
245 emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS)); in move()
270 emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) in addiu()
276 emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS) in addu()
282 emitInst(0x00000023 | (rd << OP_SH_RD) | (rs << OP_SH_RS) in subu()
288 emitInst(0x00000018 | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in mult()
293 emitInst(0x0000001a | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in div()
309 emitInst(0x70000002 | (rd << OP_SH_RD) | (rs << OP_SH_RS) in mul()
319 emitInst(0x00000024 | (rd << OP_SH_RD) | (rs << OP_SH_RS) in andInsn()
325 emitInst(0x30000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) in andi()
[all …]
/external/qemu/
Dmips-dis.c83 #define OP_SH_RS 21 macro
3606 (l >> OP_SH_RS) & OP_MASK_RS); in print_insn_args()
3681 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); in print_insn_args()