| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() argument
340 .addImm(Pred).addReg(PredReg).addReg(0); in MergeOps()
351 .addImm(Pred).addReg(PredReg); in MergeOps()
371 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate() argument
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
448 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR() argument
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
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| D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
180 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
403 unsigned PredReg; in rewriteT2FrameIndex() local
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| D | ARMBaseRegisterInfo.cpp | 710 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
720 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate() argument
752 Pred, PredReg, TII); in emitSPUpdate()
755 Pred, PredReg, TII); in emitSPUpdate()
789 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
790 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
793 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
795 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
1129 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
232 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
244 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
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| D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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| D | ARMBaseInstrInfo.h | 358 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
379 ARMCC::CondCodes Pred, unsigned PredReg,
385 ARMCC::CondCodes Pred, unsigned PredReg,
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| D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
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| D | Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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| D | Thumb2SizeReduction.cpp | 544 unsigned PredReg = 0; in ReduceSpecial() local
545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
643 unsigned PredReg = 0; in ReduceTo2Addr() local
644 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
735 unsigned PredReg = 0; in ReduceToNarrow() local
736 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0; in InsertITInstructions() local
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
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| D | Thumb1RegisterInfo.cpp | 70 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
413 unsigned PredReg; in rewriteFrameIndex() local
414 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteFrameIndex()
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| D | ARMBaseRegisterInfo.h | 169 unsigned PredReg = 0,
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| D | ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0; in ExpandMOV32BitImm() local
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
639 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
640 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
676 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
677 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
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| D | ARMConstantIslandPass.cpp | 1349 unsigned PredReg = 0; in createNewWater() local
1350 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1795 unsigned PredReg = 0; in optimizeThumb2Branches() local
1796 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1814 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
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| D | ARMBaseInstrInfo.cpp | 1535 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1538 PredReg = 0; in getInstrPredicate()
1542 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1565 unsigned PredReg = 0; in commuteInstruction() local
1566 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1568 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstruction()
1738 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
1757 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
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| D | ARMISelDAGToDAG.cpp | 2475 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2476 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2740 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2741 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2760 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2761 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2779 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2780 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 303 unsigned PredReg = LastI->getOperand(1).getReg(); in getTripCount() local
347 MI->getOperand(0).getReg() == PredReg) { in getTripCount()
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