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Searched refs:REG_SEQUENCE (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetOpcodes.h81 REG_SEQUENCE = 12, enumerator
DTarget.td737 def REG_SEQUENCE : Instruction {
/external/llvm/test/CodeGen/ARM/
D2012-01-24-RegSequenceLiveRange.ll7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
Dcrash.ll31 ; PR10520 - REG_SEQUENCE with implicit-def operands.
Dreg_sequence.ll3 ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
Dvldlane.ll500 ; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h622 return getOpcode() == TargetOpcode::REG_SEQUENCE;
658 case TargetOpcode::REG_SEQUENCE:
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp267 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
307 case TargetOpcode::REG_SEQUENCE: in reserveResources()
DInstrEmitter.cpp601 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); in EmitRegSequence()
605 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
713 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
DScheduleDAGRRList.cpp279 if (Opcode == TargetOpcode::REG_SEQUENCE) { in GetCostForDef()
2088 Opc == TargetOpcode::REG_SEQUENCE || in unscheduledNode()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp238 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
283 case TargetOpcode::REG_SEQUENCE: in reserveResources()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1452 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairSRegs()
1463 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairDRegs()
1474 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); in PairQRegs()
1490 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadSRegs()
1505 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadDRegs()
1520 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); in QuadQRegs()