| /external/llvm/test/MC/X86/ |
| D | intel-syntax.s | 9 mov DWORD PTR [RSP - 4], 257
11 mov DWORD PTR [RSP + 4], 258
13 mov QWORD PTR [RSP - 16], 123
15 mov BYTE PTR [RSP - 17], 97
17 mov EAX, DWORD PTR [RSP - 4]
19 mov RAX, QWORD PTR [RSP]
21 mov DWORD PTR [RSP - 4], -4
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
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| D | intel-syntax-2.s | 6 mov DWORD PTR [RSP - 4], 257
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| D | intel-syntax-encoding.s | 25 mov QWORD PTR [RSP - 16], RAX
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 73 StackPtr = X86::RSP; in X86RegisterInfo()
285 Reserved.set(X86::RSP); in getReservedRegs()
286 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I) in getReservedRegs()
626 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
663 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
699 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
730 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
751 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
752 return X86::RSP; in getX86SubSuperRegister()
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| D | X86InstrControl.td | 216 // RSP is marked as a use to prevent stack-pointer assignments that appear
219 let isCall = 1, Uses = [RSP] in {
242 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
243 let Defs = [RAX, R10, R11, RSP, EFLAGS],
244 Uses = [RSP] in {
253 let Uses = [RSP],
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| D | X86CompilationCallback_Win64.asm | 20 ; Save RSP.
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| D | X86RegisterInfo.td | 128 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
308 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
354 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
364 // GR64_NOSP - GR64 registers except RSP (and RIP).
365 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
372 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
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| D | X86InstrInfo.td | 264 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
756 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
815 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
834 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
843 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
846 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
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| D | X86InstrCompiler.td | 56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
389 // All calls clobber the non-callee saved registers. RSP is marked as
397 Uses = [RSP] in {
423 Uses = [RSP, RDI],
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| D | X86FrameLowering.cpp | 1467 ScratchReg = X86::RSP; in adjustForSegmentedStacks()
1469 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) in adjustForSegmentedStacks()
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| D | X86CodeEmitter.cpp | 546 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in emitMemModRMByte()
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| D | X86FastISel.cpp | 64 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; in X86FastISel()
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| D | X86ISelLowering.cpp | 161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; in X86TargetLowering()
12733 physSPReg = Is64Bit ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca()
12831 .addReg(X86::RSP, RegState::Implicit) in EmitLoweredWinAlloca()
12833 .addReg(X86::RSP, RegState::Define | RegState::Implicit) in EmitLoweredWinAlloca()
12844 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) in EmitLoweredWinAlloca()
12845 .addReg(X86::RSP) in EmitLoweredWinAlloca()
16846 case X86::SP: DestReg = X86::RSP; break; in getRegForInlineAsmConstraint()
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| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 50 #define RSP 152 macro
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 220 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
396 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
400 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
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| D | X86MCCodeEmitter.cpp | 382 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in EmitMemModRMByte()
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| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 106 GENOFFSET(AMD64,amd64,RSP); in foo()
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| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-amd64-linux.c | 360 SC2(rsp,RSP); in synth_ucontext()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 183 ENTRY(RSP) \
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| /external/llvm/docs/ |
| D | TableGenFundamentals.rst | 184 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
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| D | CodeGenerator.rst | 1445 immediately after the return address, then ``ESP/RSP`` is moved to
1446 ``EBP/RBP``. Thus to unwind, ``ESP/RSP`` is restored with the current
1469 ``ESP/RSP``. Then the return is done by popping the stack into the PC. All
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| /external/strace/ |
| D | process.c | 2693 { 8*RSP, "8*RSP" },
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| /external/valgrind/main/memcheck/ |
| D | mc_machine.c | 561 if (o == GOF(RSP) && is1248) return o; in get_otrack_shadow_offset_wrk()
|