/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCCodeEmitter.cpp | 119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 156 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument 157 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind() 158 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind() 299 uint64_t TSFlags, unsigned &CurByte, in EmitMemModRMByte() argument 327 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; in EmitMemModRMByte() 442 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, in EmitVEXOpcodePrefix() argument [all …]
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D | X86BaseInfo.h | 484 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument 485 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor() 488 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument 489 return (TSFlags & X86II::ImmMask) != 0; in hasImm() 494 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument 495 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm() 509 inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument 510 switch (TSFlags & X86II::ImmMask) { in isImmPCRel() 532 inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) { in getMemoryOperandNo() argument 533 switch (TSFlags & X86II::FormMask) { in getMemoryOperandNo() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86CodeEmitter.cpp | 70 void emitOpcodePrefix(uint64_t TSFlags, int MemOperand, 74 void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand, 78 void emitSegmentOverridePrefix(uint64_t TSFlags, 164 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) in determineREX() 166 if (Desc.TSFlags & X86II::REX_W) in determineREX() 185 switch (Desc.TSFlags & X86II::FormMask) { in determineREX() 654 void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags, in emitOpcodePrefix() argument 659 if (Desc->TSFlags & X86II::LOCK) in emitOpcodePrefix() 663 emitSegmentOverridePrefix(TSFlags, MemOperand, MI); in emitOpcodePrefix() 666 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) in emitOpcodePrefix() [all …]
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D | X86InstrFormats.td | 180 // TSFlags layout should be kept in sync with X86InstrInfo.h. 181 let TSFlags{5-0} = FormBits; 182 let TSFlags{6} = hasOpSizePrefix; 183 let TSFlags{7} = hasAdSizePrefix; 184 let TSFlags{12-8} = Prefix; 185 let TSFlags{13} = hasREX_WPrefix; 186 let TSFlags{16-14} = ImmT.Value; 187 let TSFlags{19-17} = FPForm.Value; 188 let TSFlags{20} = hasLockPrefix; 189 let TSFlags{22-21} = SegOvrBits; [all …]
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXInstrFormats.td | 39 let TSFlags{3-0} = VecInstType; 40 let TSFlags{4-4} = IsSimpleMove; 41 let TSFlags{5-5} = IsLoad; 42 let TSFlags{6-6} = IsStore;
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D | NVPTXInstrInfo.cpp | 119 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> in isMoveInstr() local 121 isMove = (TSFlags == 1); in isMoveInstr() 162 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> in isLoadInstr() local 164 isLoad = (TSFlags == 1); in isLoadInstr() 173 unsigned TSFlags = (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> in isStoreInstr() local 175 isStore = (TSFlags == 1); in isStoreInstr()
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D | VectorElementize.cpp | 133 #define VECINST(x) ((((x)->getDesc().TSFlags) & NVPTX::VecInstTypeMask) \ 147 unsigned TSFlags = (mi->getDesc().TSFlags & NVPTX::SimpleMoveMask) in isSimpleMove() local 149 return (TSFlags == 1); in isSimpleMove()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCHazardRecognizers.cpp | 99 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local 101 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType() 102 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType() 103 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType() 104 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
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D | PPCInstrFormats.td | 34 let TSFlags{0} = PPC970_First; 35 let TSFlags{1} = PPC970_Single; 36 let TSFlags{2} = PPC970_Cracked; 37 let TSFlags{5-3} = PPC970_Unit; 79 let TSFlags{0} = PPC970_First; 80 let TSFlags{1} = PPC970_Single; 81 let TSFlags{2} = PPC970_Cracked; 82 let TSFlags{5-3} = PPC970_Unit;
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/external/llvm/lib/Target/ARM/ |
D | ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard() 44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType() 51 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
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D | ARMCodeEmitter.cpp | 483 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) in getMachineOpValue() 563 switch (MI.getDesc().TSFlags & ARMII::FormMask) { in emitInstruction() 1162 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; in emitDataProcessingInstruction() 1175 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { in emitDataProcessingInstruction() 1197 unsigned Form = MCID.TSFlags & ARMII::FormMask; in emitLoadStoreInstruction() 1198 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; in emitLoadStoreInstruction() 1281 unsigned Form = MCID.TSFlags & ARMII::FormMask; in emitMiscLoadStoreInstruction() 1282 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; in emitMiscLoadStoreInstruction() 1366 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; in emitLoadStoreMultipleInstruction() 1722 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) in emitVFPArithInstruction() [all …]
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D | MLxExpansionPass.cpp | 141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard() 286 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
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D | ARMBaseRegisterInfo.cpp | 805 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset() 996 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal() 1121 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex() 1122 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && in eliminateFrameIndex()
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D | ARMBaseInstrInfo.cpp | 127 uint64_t TSFlags = MI->getDesc().TSFlags; in convertToThreeAddress() local 129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { in convertToThreeAddress() 146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in convertToThreeAddress() 526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { in isPredicable() 1768 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteARMFrameIndex() 3273 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; in hasHighOperandLatency() 3274 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; in hasHighOperandLatency() 3297 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; in hasLowDefLatency() 3366 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; in getExecutionDomain()
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/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
D | MBlazeMCCodeEmitter.cpp | 182 uint64_t TSFlags = Desc.TSFlags; in EncodeInstruction() local 189 switch ((TSFlags & MBlazeII::FormMask)) { in EncodeInstruction()
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsMCCodeEmitter.cpp | 125 uint64_t TSFlags = Desc.TSFlags; in EncodeInstruction() local 129 if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo) in EncodeInstruction()
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/external/llvm/lib/Target/Mips/ |
D | MipsCodeEmitter.cpp | 159 uint64_t TSFlags = MI.getDesc().TSFlags; in getRelocation() local 160 uint64_t Form = TSFlags & MipsII::FormMask; in getRelocation() 383 if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) in emitInstruction()
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D | MipsInstrFormats.td | 67 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 68 let TSFlags{3-0} = FormBits;
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D | Mips16InstrFormats.td | 86 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 87 let TSFlags{4-0} = FormBits;
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrFormats.td | 51 let TSFlags{4-0} = HexagonType.Value; 54 let TSFlags{5} = isHexagonSolo; 57 let TSFlags{6} = isPredicated;
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/external/llvm/include/llvm/MC/ |
D | MCInstrDesc.h | 142 uint64_t TSFlags; // Target Specific Flag values variable
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/external/llvm/lib/Target/MBlaze/ |
D | MBlazeInstrFormats.td | 77 // TSFlags layout should be kept in sync with MBlazeInstrInfo.h. 78 let TSFlags{5-0} = FormBits;
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/external/llvm/lib/Target/MSP430/ |
D | MSP430InstrFormats.td | 68 let TSFlags{1-0} = Form.Value; 69 let TSFlags{4-2} = Sz.Value;
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D | MSP430InstrInfo.cpp | 295 switch (Desc.TSFlags & MSP430II::SizeMask) { in GetInstSizeInBytes()
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 1493 uint64_t TSFlags = Desc.TSFlags; in EncodeInstruction() local 1494 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) in EncodeInstruction()
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