Searched refs:VG_IS_4_ALIGNED (Results 1 – 6 of 6) sorted by relevance
82 CHECK( VG_IS_4_ALIGNED(0x0) ); in test_VG_IS_XYZ_ALIGNED()83 CHECK( ! VG_IS_4_ALIGNED(0x1) ); in test_VG_IS_XYZ_ALIGNED()84 CHECK( ! VG_IS_4_ALIGNED(0x2) ); in test_VG_IS_XYZ_ALIGNED()85 CHECK( ! VG_IS_4_ALIGNED(0x3) ); in test_VG_IS_XYZ_ALIGNED()86 CHECK( VG_IS_4_ALIGNED(0x4) ); in test_VG_IS_XYZ_ALIGNED()87 CHECK( ! VG_IS_4_ALIGNED(0x5) ); in test_VG_IS_XYZ_ALIGNED()88 CHECK( ! VG_IS_4_ALIGNED(0x6) ); in test_VG_IS_XYZ_ALIGNED()89 CHECK( ! VG_IS_4_ALIGNED(0x7) ); in test_VG_IS_XYZ_ALIGNED()90 CHECK( VG_IS_4_ALIGNED(0x8) ); in test_VG_IS_XYZ_ALIGNED()91 CHECK( ! VG_IS_4_ALIGNED(0x9) ); in test_VG_IS_XYZ_ALIGNED()[all …]
1149 && nBits == 32 && VG_IS_4_ALIGNED(a))) { in mc_LOADVn_slow()1240 && nBits == 32 && VG_IS_4_ALIGNED(a))) { in mc_STOREVn_slow()1627 aligned = VG_IS_4_ALIGNED(src) && VG_IS_4_ALIGNED(dst); in MC_()2514 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_4_w_ECU()2525 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_4()2536 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_die_mem_stack_4()2552 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_8_w_ECU()2566 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_8()2580 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_die_mem_stack_8()2598 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_12_w_ECU()[all …]
539 if (VG_IS_4_ALIGNED(dI) && VG_IS_4_ALIGNED(sI)) { in VG_()591 while ((!VG_IS_4_ALIGNED(d)) && sz >= 1) { in VG_()
161 #define VG_IS_4_ALIGNED(aaa_p) (0 == (((Addr)(aaa_p)) & ((Addr)0x3))) macro
3441 if (UNLIKELY( !VG_IS_4_ALIGNED(a) )) in Filter__ok_to_skip_crd32()3556 if (UNLIKELY( !VG_IS_4_ALIGNED(a) )) in Filter__ok_to_skip_cwr32()
2132 vg_assert(di && VG_IS_4_ALIGNED(di)); in find_DiCfSI()