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Searched refs:Writeback (Results 1 – 14 of 14) sorted by relevance

/external/clang/lib/CodeGen/
DCGCall.h61 struct Writeback { struct
84 Writeback writeback; in addWriteback() argument
93 typedef SmallVectorImpl<Writeback>::const_iterator writeback_iterator;
98 SmallVector<Writeback, 1> Writebacks;
DCGCall.cpp1639 const CallArgList::Writeback &writeback) { in emitWriteback()
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-LDM-thumb.txt3 # Writeback is not allowed is Rn is in the target register list.
/external/clang/test/SemaObjCXX/
Darc-overloading.mm57 // Writeback conversion
72 // Writeback conversion vs. no conversion
88 // Writeback conversion vs. other conversion.
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp191 bool Writeback = true; in printInst() local
195 Writeback = false; in printInst()
202 if (Writeback) O << "!"; in printInst()
/external/oprofile/events/x86-64/hammer/
Dunit_masks156 0x01 Victim Block (Writeback)
/external/oprofile/events/x86-64/family11h/
Dunit_masks162 0x01 Victim Block (Writeback)
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td143 let Inst{21} = 1; // Writeback
152 let Inst{21} = 1; // Writeback
175 let Inst{21} = 1; // Writeback
188 let Inst{21} = 1; // Writeback
DARMInstrThumb.td700 // Writeback version is just a pseudo, as there's no encoding difference.
701 // Writeback happens iff the base register is not in the destination register
DARMInstrThumb2.td1614 let Inst{21} = 1; // Writeback
1644 let Inst{21} = 1; // Writeback
1686 let Inst{21} = 1; // Writeback
1722 let Inst{21} = 1; // Writeback
DARMInstrInfo.td2721 let Inst{21} = 1; // Writeback
2741 let Inst{21} = 1; // Writeback
2761 let Inst{21} = 1; // Writeback
2781 let Inst{21} = 1; // Writeback
/external/oprofile/events/x86-64/family10/
Dunit_masks175 0x01 Victim Block (Writeback)
/external/regex-re2/benchlog/
Dbenchlog.r7035 Writeback: 0 kB
/external/qemu/
Dqemu-options.hx136 Writeback caching will report data writes as completed as soon as the data is