Searched refs:hasSubClassEq (Results 1 – 9 of 9) sorted by relevance
165 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()167 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()169 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()171 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()173 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()192 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()194 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()196 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()200 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
449 if (PPC::GPRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()465 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()481 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()486 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()491 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()533 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()567 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()617 if (PPC::GPRCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()626 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()635 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in LoadRegFromStackSlot()[all …]
125 return RC != this && hasSubClassEq(RC); in hasSubClass()130 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function144 return RC->hasSubClassEq(this); in hasSuperClassEq()
773 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()777 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()785 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()793 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()810 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()830 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()852 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()947 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()951 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()958 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()[all …]
51 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
2710 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()2711 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()2712 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()2863 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()2867 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()2871 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()2874 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()2876 if (X86::FR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()2880 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()2884 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()[all …]
274 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
369 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()373 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()377 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
540 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()