Searched refs:isLd (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 865 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD; in MergeBaseUpdateLoadStore() local
868 if (isLd && MI->getOperand(0).getReg() == Base) in MergeBaseUpdateLoadStore()
932 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
934 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
936 } else if (isLd) { in MergeBaseUpdateLoadStore()
1117 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1118 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1121 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1135 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1138 if (isLd) { in FixInvalidRegPairOp()
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| D | ARMInstrFormats.td | 565 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
575 let Inst{20} = isLd;
578 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
588 let Inst{20} = isLd; // L bit
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