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/external/llvm/test/CodeGen/X86/
D2009-11-13-VirtRegRewriterBug.ll9 %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; <i640> [#uses=1]
31 %mask271.masked.masked.masked.masked.masked.masked.masked = or i256 0, undef ; <i256> [#uses=2]
32 …%mask266.masked.masked.masked.masked.masked.masked = or i256 %mask271.masked.masked.masked.masked.…
33 %mask241.masked = or i256 undef, undef ; <i256> [#uses=1]
53 …%tmp211 = lshr i256 %mask271.masked.masked.masked.masked.masked.masked.masked, 112 ; <i256> [#uses…
55 %tmp208 = lshr i256 %mask266.masked.masked.masked.masked.masked.masked, 128 ; <i256> [#uses=1]
60 %tmp193 = lshr i256 %mask241.masked, 208 ; <i256> [#uses=1]
97 %tmp101 = lshr i640 %mask133.masked.masked.masked.masked.masked.masked, 256 ; <i640> [#uses=1]
Dnarrow-shl-load.ll19 %shl15.masked = and i64 %shl15, 4294967294
20 %and17 = or i64 %shl15.masked, %conv11
/external/llvm/test/CodeGen/PowerPC/
Drlwinm2.ll25 %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1]
26 %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1]
/external/llvm/test/CodeGen/Thumb2/
Dbfi.ll58 %b.masked = and i32 %b, -2
59 %and3 = or i32 %b.masked, %and
/external/oprofile/events/i386/athlon/
Devents24 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED : Interrupts masked cycles (…
25 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_PENDING : Interrupts masked …
/external/llvm/test/CodeGen/ARM/
D2009-10-21-InvalidFNeg.ll28 %mask.masked = or i512 %tmp124, %tmp100 ; <i512> [#uses=1]
38 %tmp86 = lshr i512 %mask.masked, 256 ; <i512> [#uses=1]
Dfpcmp-opt.ll28 ; If one side is zero, the other size sign bit is masked off to allow
D2008-04-11-PHIofImpDef.ll2905 %tmp4253.masked.i = and i32 %tmp4253.i, 65535 ; <i32> [#uses=1]
2910 %tmp4262.masked.i = and i32 %tmp4262.i188, 64512 ; <i32> [#uses=1]
2911 %tmp42665693.masked.i = or i32 %tmp4262.masked.i, %tmp4210.i ; <i32> [#uses=1]
2914 …%tmp42665693.masked.pn.i = phi i32 [ %tmp42665693.masked.i, %bb4259.i ], [ %tmp4253.masked.i, %bb4…
2916 %tmp100.0.i = or i32 %tmp4268.pn.i, %tmp42665693.masked.pn.i ; <i32> [#uses=0]
/external/valgrind/main/gdbserver_tests/
Dnlsigvgdb.vgtest4 # But if this signal is masked, then vgdb does not recuperate the control
/external/elfutils/libcpu/
Di386_disasm.c405 uint_fast8_t masked = *codep++ & *curr++; in i386_disasm() local
406 if (masked != *curr++) in i386_disasm()
/external/oprofile/events/x86-64/hammer/
Devents89 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
90 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
/external/oprofile/events/x86-64/family11h/
Devents94 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
95 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
/external/valgrind/main/docs/internals/
Darm_thumb_notes_gdbserver.txt27 must be masked.
/external/chromium/chrome/browser/ui/gtk/
Dgtk_theme_service.cc212 SkBitmap masked = SkBitmapOperations::CreateMaskedBitmap( in BuildIconFromIDRWithColor() local
216 GdkPixbuf* pixbuf = gfx::GdkPixbufFromSkBitmap(&masked); in BuildIconFromIDRWithColor()
/external/bison/tests/
Dconflicts.at347 # In this precise case (a reduction is masked by the default
/external/oprofile/events/x86-64/family10/
Devents112 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
113 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
/external/llvm/lib/Target/PowerPC/
DREADME.txt565 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
566 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
/external/mesa3d/src/glsl/
DREADME141 If every masked update of a component relies on the previous value of
/external/oprofile/events/i386/nehalem/
Dunit_masks78 0x02 cycles_masked Number of cycles interrupt are masked
79 0x04 cycles_pending_and_masked Number of cycles interrupts are pending and masked
/external/llvm/lib/Target/
DREADME.txt1550 %.masked = and i8 %a, 64 ; <i8> [#uses=1]
1553 %3 = or i8 %2, %.masked ; <i8> [#uses=1]
/external/valgrind/main/VEX/priv/
Dguest_arm_toIR.c947 IRTemp masked = newTemp(Ity_I32); in put_GEFLAG32() local
948 assign(masked, binop(Iop_Shr32, e, mkU8(lowbits_to_ignore))); in put_GEFLAG32()
951 case 0: putMiscReg32(OFFB_GEFLAG0, mkexpr(masked), condT); break; in put_GEFLAG32()
952 case 1: putMiscReg32(OFFB_GEFLAG1, mkexpr(masked), condT); break; in put_GEFLAG32()
953 case 2: putMiscReg32(OFFB_GEFLAG2, mkexpr(masked), condT); break; in put_GEFLAG32()
954 case 3: putMiscReg32(OFFB_GEFLAG3, mkexpr(masked), condT); break; in put_GEFLAG32()
/external/webkit/Source/WebKit/efl/
DChangeLog1459 At this time we cannot test this change since it is being masked by
/external/srtp/doc/
Drfc3711.txt1281 under another key to produce an internal, "masked" value (denoted
/external/webkit/Source/WebKit/win/
DChangeLog2423 At this time we cannot test this change since it is being masked by
/external/stlport/etc/
DChangeLog-5.18190 * stl_sunpro.h : strstream masked for CC 4.2 to avoid virtual table clash (thanks to Ken)

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