Home
last modified time | relevance | path

Searched refs:offsetof (Results 1 – 25 of 224) sorted by relevance

123456789

/external/libvpx/vp8/encoder/
Dasm_enc_offsets.c37 DEFINE(vp8_block_coeff, offsetof(BLOCK, coeff));
38 DEFINE(vp8_block_zbin, offsetof(BLOCK, zbin));
39 DEFINE(vp8_block_round, offsetof(BLOCK, round));
40 DEFINE(vp8_block_quant, offsetof(BLOCK, quant));
41 DEFINE(vp8_block_quant_fast, offsetof(BLOCK, quant_fast));
42 DEFINE(vp8_block_zbin_extra, offsetof(BLOCK, zbin_extra));
43 DEFINE(vp8_block_zrun_zbin_boost, offsetof(BLOCK, zrun_zbin_boost));
44 DEFINE(vp8_block_quant_shift, offsetof(BLOCK, quant_shift));
46 DEFINE(vp8_blockd_qcoeff, offsetof(BLOCKD, qcoeff));
47 DEFINE(vp8_blockd_dequant, offsetof(BLOCKD, dequant));
[all …]
/external/libvpx/vp8/decoder/
Dasm_dec_offsets.c28 DEFINE(detok_scan, offsetof(DETOK, scan));
29 DEFINE(detok_ptr_block2leftabove, offsetof(DETOK, ptr_block2leftabove));
30 DEFINE(detok_coef_tree_ptr, offsetof(DETOK, vp8_coef_tree_ptr));
31 DEFINE(detok_teb_base_ptr, offsetof(DETOK, teb_base_ptr));
32 DEFINE(detok_norm_ptr, offsetof(DETOK, norm_ptr));
33 DEFINE(detok_ptr_coef_bands_x, offsetof(DETOK, ptr_coef_bands_x));
35 DEFINE(detok_A, offsetof(DETOK, A));
36 DEFINE(detok_L, offsetof(DETOK, L));
38 DEFINE(detok_qcoeff_start_ptr, offsetof(DETOK, qcoeff_start_ptr));
39 DEFINE(detok_current_bc, offsetof(DETOK, current_bc));
[all …]
/external/clang/test/CodeGen/
Darm-apcs-zerolength-bitfield.c16 static int arr1_offset[(offsetof(struct t1, bar) == 4) ? 0 : -1];
25 static int arr2_offset[(offsetof(struct t2, bar) == 4) ? 0 : -1];
34 static int arr3_offset[(offsetof(struct t3, bar) == 4) ? 0 : -1];
43 static int arr4_offset[(offsetof(struct t4, bar) == 4) ? 0 : -1];
52 static int arr5_offset[(offsetof(struct t5, bar) == 4) ? 0 : -1];
62 static int arr6_offset[(offsetof(struct t6, bar2) == 5) ? 0 : -1];
72 static int arr7_offset[(offsetof(struct t7, bar2) == 5) ? 0 : -1];
82 static int arr8_offset[(offsetof(struct t8, bar2) == 5) ? 0 : -1];
92 static int arr9_offset[(offsetof(struct t9, bar2) == 5) ? 0 : -1];
102 static int arr10_offset[(offsetof(struct t10, bar2) == 5) ? 0 : -1];
[all …]
Darm-aapcs-zerolength-bitfield.c12 static int arr1_offset[(offsetof(struct t1, bar) == 1) ? 0 : -1];
21 static int arr2_offset[(offsetof(struct t2, bar) == 2) ? 0 : -1];
30 static int arr3_offset[(offsetof(struct t3, bar) == 4) ? 0 : -1];
39 static int arr4_offset[(offsetof(struct t4, bar) == 4) ? 0 : -1];
48 static int arr5_offset[(offsetof(struct t5, bar) == 8) ? 0 : -1];
58 static int arr6_offset[(offsetof(struct t6, bar2) == 2) ? 0 : -1];
68 static int arr7_offset[(offsetof(struct t7, bar2) == 3) ? 0 : -1];
78 static int arr8_offset[(offsetof(struct t8, bar2) == 5) ? 0 : -1];
88 static int arr9_offset[(offsetof(struct t9, bar2) == 5) ? 0 : -1];
98 static int arr10_offset[(offsetof(struct t10, bar2) == 9) ? 0 : -1];
[all …]
/external/oprofile/libabi/
Dop_abi.c37 { "offsetof_node_key", offsetof(odb_node_t, key) },
38 { "offsetof_node_value", offsetof(odb_node_t, value) },
39 { "offsetof_node_next", offsetof(odb_node_t, next) },
41 { "offsetof_descr_size", offsetof(odb_descr_t, size) },
42 { "offsetof_descr_current_size", offsetof(odb_descr_t, current_size) },
44 { "offsetof_header_magic", offsetof(struct opd_header, magic) },
45 { "offsetof_header_version", offsetof(struct opd_header, version) },
46 { "offsetof_header_cpu_type", offsetof(struct opd_header, cpu_type) },
47 { "offsetof_header_ctr_event", offsetof(struct opd_header, ctr_event) },
48 { "offsetof_header_ctr_um", offsetof(struct opd_header, ctr_um) },
[all …]
/external/qemu/
Dmonitor.c1857 { name, offsetof(CPUState, segs[seg].selector), NULL, MD_I32 },\
1858 { name ".base", offsetof(CPUState, segs[seg].base) },\
1859 { name ".limit", offsetof(CPUState, segs[seg].limit), NULL, MD_I32 },
1861 { "eax", offsetof(CPUState, regs[0]) },
1862 { "ecx", offsetof(CPUState, regs[1]) },
1863 { "edx", offsetof(CPUState, regs[2]) },
1864 { "ebx", offsetof(CPUState, regs[3]) },
1865 { "esp|sp", offsetof(CPUState, regs[4]) },
1866 { "ebp|fp", offsetof(CPUState, regs[5]) },
1867 { "esi", offsetof(CPUState, regs[6]) },
[all …]
Dgen-icount.h17 tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32)); in gen_icount_start()
23 tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low)); in gen_icount_start()
39 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_start()
46 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_end()
/external/valgrind/main/coregrind/
Dm_vki.c116 vg_assert(offsetof(t1,sa_handler) == offsetof(t2.ksa_handler)); in VG_()
117 vg_assert(offsetof(t1.sa_tramp) == offsetof(t2.sa_tramp)); in VG_()
118 vg_assert(offsetof(t1.sa_mask) == offsetof(t2.sa_mask)); in VG_()
119 vg_assert(offsetof(t1.sa_flags) == offsetof(t2.sa_flags)); in VG_()
120 vg_assert(offsetof(f1.sa_handler) == offsetof(f2.ksa_handler)); in VG_()
121 vg_assert(offsetof(f1.sa_mask) == offsetof(f2.sa_mask)); in VG_()
122 vg_assert(offsetof(f1.sa_flags) == offsetof(f2.sa_flags)); in VG_()
/external/libvpx/vp8/common/
Dasm_com_offsets.c33 DEFINE(yv12_buffer_config_y_width, offsetof(YV12_BUFFER_CONFIG, y_width));
34 DEFINE(yv12_buffer_config_y_height, offsetof(YV12_BUFFER_CONFIG, y_height));
35 DEFINE(yv12_buffer_config_y_stride, offsetof(YV12_BUFFER_CONFIG, y_stride));
36 DEFINE(yv12_buffer_config_uv_width, offsetof(YV12_BUFFER_CONFIG, uv_width));
37 DEFINE(yv12_buffer_config_uv_height, offsetof(YV12_BUFFER_CONFIG, uv_height));
38 DEFINE(yv12_buffer_config_uv_stride, offsetof(YV12_BUFFER_CONFIG, uv_stride));
39 DEFINE(yv12_buffer_config_y_buffer, offsetof(YV12_BUFFER_CONFIG, y_buffer));
40 DEFINE(yv12_buffer_config_u_buffer, offsetof(YV12_BUFFER_CONFIG, u_buffer));
41 DEFINE(yv12_buffer_config_v_buffer, offsetof(YV12_BUFFER_CONFIG, v_buffer));
42 DEFINE(yv12_buffer_config_border, offsetof(YV12_BUFFER_CONFIG, border));
/external/clang/test/Sema/
Dpragma-align-mac68k.c17 extern int a1_0[offsetof(struct s1, f0) == 0 ? 1 : -1];
18 extern int a1_1[offsetof(struct s1, f1) == 2 ? 1 : -1];
26 extern int a2_0[offsetof(struct s2, f0) == 0 ? 1 : -1];
27 extern int a2_1[offsetof(struct s2, f1) == 2 ? 1 : -1];
35 extern int a3_0[offsetof(struct s3, f0) == 0 ? 1 : -1];
36 extern int a3_1[offsetof(struct s3, f1) == 2 ? 1 : -1];
44 extern int a4_0[offsetof(struct s4, f0) == 0 ? 1 : -1];
45 extern int a4_1[offsetof(struct s4, f1) == 1 ? 1 : -1];
95 extern int a11_0[offsetof(struct s11, f0) == 0 ? 1 : -1];
96 extern int a11_1[offsetof(struct s11, f1) == 2 ? 1 : -1];
Dpragma-pack-2.c12 extern int a0[offsetof(struct s0, f1) == 4 ? 1 : -1];
19 extern int a1[offsetof(struct s1, f1) == 2 ? 1 : -1];
32 extern int a3_0[offsetof(struct s3_0, f1) == 1 ? 1 : -1];
33 extern int a3_1[offsetof(struct s3_1, f1) == 4 ? 1 : -1];
46 extern int a4_0[offsetof(struct s4_0, f1) == 1 ? 1 : -1];
47 extern int a4_1[offsetof(struct s4_1, f1) == 4 ? 1 : -1];
58 extern int s5_0[offsetof(struct s5_0, f1) == 2 ? 1 : -1]; in f()
Doffsetof.c3 #define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) macro
17 x = offsetof(struct external_sun3_core, c_regs); in swap()
31 int v1 = offsetof (struct s1, a) == 0 ? 0 : f();
/external/elfutils/libelf/
Delf_end.c140 || (offsetof (struct Elf, state.elf32.rawchunks)
141 == offsetof (struct Elf, state.elf64.rawchunks))
154 || (offsetof (struct Elf, state.elf32.scns)
155 == offsetof (struct Elf, state.elf64.scns))
205 || (offsetof (struct Elf, state.elf32.scns)
206 == offsetof (struct Elf, state.elf64.scns))
217 || (offsetof (struct Elf, state.elf32.shdr)
218 == offsetof (struct Elf, state.elf64.shdr))
225 || (offsetof (struct Elf, state.elf32.phdr)
226 == offsetof (struct Elf, state.elf64.phdr))
Delf_newscn.c76 assert (offsetof (Elf, state.elf.scns_last)
77 == offsetof (Elf, state.elf32.scns_last));
78 assert (offsetof (Elf, state.elf.scns_last)
79 == offsetof (Elf, state.elf64.scns_last));
80 assert (offsetof (Elf, state.elf32.scns)
81 == offsetof (Elf, state.elf64.scns));
93 || (offsetof (Elf, state.elf32.scns)
94 == offsetof (Elf, state.elf64.scns))
Delf_getshstrndx.c86 assert (offsetof (struct Elf, state.elf.ehdr)
87 == offsetof (struct Elf, state.elf32.ehdr));
90 assert (offsetof (struct Elf, state.elf.ehdr)
91 == offsetof (struct Elf, state.elf64.ehdr));
/external/qemu/hw/
Dsmbios.c118 smbios_add_field(0, offsetof(struct smbios_type_0, vendor_str), in smbios_build_type_0_fields()
121 smbios_add_field(0, offsetof(struct smbios_type_0, bios_version_str), in smbios_build_type_0_fields()
124 smbios_add_field(0, offsetof(struct smbios_type_0, in smbios_build_type_0_fields()
130 smbios_add_field(0, offsetof(struct smbios_type_0, in smbios_build_type_0_fields()
132 smbios_add_field(0, offsetof(struct smbios_type_0, in smbios_build_type_0_fields()
142 smbios_add_field(1, offsetof(struct smbios_type_1, manufacturer_str), in smbios_build_type_1_fields()
145 smbios_add_field(1, offsetof(struct smbios_type_1, product_name_str), in smbios_build_type_1_fields()
148 smbios_add_field(1, offsetof(struct smbios_type_1, version_str), in smbios_build_type_1_fields()
151 smbios_add_field(1, offsetof(struct smbios_type_1, serial_number_str), in smbios_build_type_1_fields()
160 smbios_add_field(1, offsetof(struct smbios_type_1, sku_number_str), in smbios_build_type_1_fields()
[all …]
/external/qemu/target-i386/
Dtranslate.c279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); in gen_op_mov_reg_v()
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); in gen_op_mov_reg_v()
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_v()
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in gen_op_mov_reg_v()
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_mov_reg_v()
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_A0()
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_A0()
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in gen_op_mov_reg_A0()
[all …]
Dop_helper.c1198 uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); in handle_even_inj()
1208 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err), error_code); in handle_even_inj()
1210 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), event_inj); in handle_even_inj()
1277 uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); in do_interrupt()
1278 … stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), event_inj & ~SVM_EVTINJ_VALID); in do_interrupt()
4904 stw_phys(addr + offsetof(struct vmcb_seg, selector), in svm_save_seg()
4906 stq_phys(addr + offsetof(struct vmcb_seg, base), in svm_save_seg()
4908 stl_phys(addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
4910 stw_phys(addr + offsetof(struct vmcb_seg, attrib), in svm_save_seg()
4918 sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector)); in svm_load_seg()
[all …]
/external/valgrind/main/memcheck/tests/linux/
Dsigqueue.c19 offsetof(siginfo_t, si_signo)); in main()
21 offsetof(siginfo_t, si_errno)); in main()
23 offsetof(siginfo_t, si_code)); in main()
25 offsetof(siginfo_t, _sifields)); in main()
/external/chromium/net/base/
Dx509_cert_types_mac.cc55 { SEC_ASN1_CHOICE, offsetof(KeyValuePair, value_type), },
57 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypePrintableString },
59 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypeIA5String },
61 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypeT61String },
63 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypeUTF8String },
65 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypeBMPString },
67 offsetof(KeyValuePair, value), 0, KeyValuePair::kTypeUniversalString },
73 { SEC_ASN1_OBJECT_ID, offsetof(KeyValuePair, key), },
83 { SEC_ASN1_SET_OF, offsetof(KeyValuePairs, pairs),
92 { SEC_ASN1_SEQUENCE_OF, offsetof(X509Name, pairs_list),
/external/kernel-headers/original/linux/
Dstddef.h20 #undef offsetof
22 #define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) macro
24 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) macro
/external/iptables/libiptc/
Dlinux_stddef.h11 #undef offsetof
12 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) macro
25 (type *)( (char *)__mptr - offsetof(type,member) );})
/external/blktrace/
Drbtree.h113 #undef offsetof
115 #define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) macro
117 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) macro
122 (type *)( (char *)__mptr - offsetof(type,member) );})
/external/valgrind/main/VEX/priv/
Dguest_ppc_helpers.c686 Int lr_min = offsetof(VexGuestPPC32State, guest_LR); in guest_ppc32_state_requires_precise_mem_exns()
688 Int r1_min = offsetof(VexGuestPPC32State, guest_GPR1); in guest_ppc32_state_requires_precise_mem_exns()
690 Int cia_min = offsetof(VexGuestPPC32State, guest_CIA); in guest_ppc32_state_requires_precise_mem_exns()
721 Int lr_min = offsetof(VexGuestPPC64State, guest_LR); in guest_ppc64_state_requires_precise_mem_exns()
723 Int r1_min = offsetof(VexGuestPPC64State, guest_GPR1); in guest_ppc64_state_requires_precise_mem_exns()
725 Int r2_min = offsetof(VexGuestPPC64State, guest_GPR2); in guest_ppc64_state_requires_precise_mem_exns()
727 Int cia_min = offsetof(VexGuestPPC64State, guest_CIA); in guest_ppc64_state_requires_precise_mem_exns()
759 { offsetof(VexGuestPPC32State, field), \
769 .offset_SP = offsetof(VexGuestPPC32State,guest_GPR1),
773 .offset_FP = offsetof(VexGuestPPC32State,guest_GPR1),
[all …]
/external/qemu/target-mips/
Dtranslate.c557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_load_srsgpr()
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_store_srsgpr()
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_load_fpr32()
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_store_fpr32()
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_load_fpr32h()
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_store_fpr32h()
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); in gen_load_fpr64()
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); in gen_store_fpr64()
922 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
923 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
[all …]

123456789