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Searched refs:reg_end (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/CodeGen/
DSpiller.cpp93 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { in trivialSpillEverywhere()
103 } while (regItr != mri->reg_end() && (&*regItr == mi)); in trivialSpillEverywhere()
DPHIEliminationUtils.cpp38 RE = MRI.reg_end(); RI != RE; ++RI) { in findPHICopyInsertPoint()
DMachineRegisterInfo.cpp190 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { in replaceRegWith()
DTwoAddressInstructionPass.cpp312 E = MRI->reg_end(); I != E; ++I) { in NoUseAfterLastDef()
1480 RE = MRI->reg_end(); RI != RE; ) { in UpdateRegSequenceSrcs()
DLiveInterval.cpp868 RE = MRI.reg_end(); RI != RE;) { in Distribute()
DScheduleDAGInstrs.cpp157 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) { in clear()
DSplitKit.cpp971 RE = MRI.reg_end(); RI != RE;) { in rewriteAssigned()
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h173 static reg_iterator reg_end() { return reg_iterator(0); } in reg_end() function
177 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } in reg_empty()
DScheduleDAGInstrs.h135 const_iterator reg_end() const { return PhysRegSet.end(); } in reg_end() function
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp332 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end(); in getTripCount()
/external/llvm/lib/Target/PowerPC/
DPPCCTRLoops.cpp341 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end(); in getTripCount()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp860 if (RI == RegInfo->reg_end()) in TryToFoldFastISelLoad()
868 if (PostRI != RegInfo->reg_end()) in TryToFoldFastISelLoad()